Datasheet > CYDD04S72V18-200BBC

CYDD04S72V18-200BBC

更新时间： 2023-07-15 00:00:00

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
48页	959K
描述
Dual-Port SRAM, 64KX72, 9ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484

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PRELIMINARY

FullFlex

Document History Page

Document Title: FullFlex™ Synchronous DDR Dual-Port SRAM

Document Number: 38-06072

Issue

Date

274729 See ECN

Orig. of

Change

SPN

REV.

ECN NO.

Description of Change

New data sheet

294239 See ECN

SPN

Updated VIM section

Added notes 7

Added timing for 100 MHz with DLL Disabled

Removed t_PS

301331 See ECN

318834 See ECN

SPN

Added note 19

Updates Selectable I/O Standard Section

Updated Block Diagram

Updated 484 pinouts, changed pins D11, W12, K3, K20

Added note 4 - Leaving pin NC disables VIM

Updated 256 pinout, changed pins C10, G5, N7, N10

Added note 18, 19, 20, 21

Updated parameters in table 16

Updated note 1

386692 See ECN

SPN

Updated ordering information

Added statement about no echo clocks for flow-through mode

Updated electrical characteristics

Added note 27 (timing for x18 devices)

Updated address readback latency to 2 cycles for DDR mode

Updated DDR timing numbers for t_CD, t_DC, t_CCQ, t_CQHQV, t_CQHQX, t_CKHZ, t_CKLZ

Updated input edge rate

Removed -133 speed bin electrical characteristics and timing columns

Updated Table 5 on collision detection to be the same as the one found in the EROS

Added description of busy readback in collision detection section

Changed dummy write descriptions

Updated PORTSTD[1:0] connection details

Updated ZQ pins connection details

Updated address count notes

Updated note 17, BO to BEO

Added power supply requirements to MRST and VC_SEL

Updated 484 ball package

Changed name from FLEX72-E, FLEX36-E, AND FLEX18-E to FullFlex72,

FullFlex36, and FullFlex18

401662 See ECN

KGH

Updated READY description to include Wired OR note

Updated master reset to include wired OR note for READY

Updated electrical characteristics to include I_OHand I_OLvalues

Updated electrical characteristics to include READY

Added I_IX3

Updated maximum input capacitance

Added note 29

Updated Pin Definitions for CQ0, CQ0, CQ1, and CQ1

Changed voltage name from VDDQ to VDDIO

Changed voltage name from V_DDto V_CORE

Updated the Package Type for the CYDXXS36V18 parts

Updated the Package Type for the CYDXXS18V18 parts

Included the Package Diagram for the 256-Ball FBGA (19 x 19 mm) BW256

Included an OE Controlled Write for Flow-Through Mode Switching Waveform

Included a Read with Echo Clock Switching Waveform

Included a Unit column for Table 5

Removed Switching Characteristic t_CAfrom chart

Included t_OHZin Switching Waveform OE Controlled Write for Pipelined Mode

Included t_CKLZ2in Waveform Read-to-Write-to-Read for Flow-Through Mode

Updated AC Test Load and Waveforms

Included FullFlex36 DDR 484-ball BGA Pinout (Top View)

Included FullFlex18 DDR 484-ball BGA Pinout (Top View)Included Timing

Parameter t_CORDY

Document #: 38-06072 Rev. *E

Page 48 of 48

1...45 46 4748

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与CYDD04S72V18-200BBC相关器件

型号	品牌	描述	获取价格	数据表
CYDD04S72V18-200BBI	CYPRESS	Dual-Port SRAM, 64KX72, 9ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLASTI	获取价格
CYDD04S72V18-200BGXC	CYPRESS	Dual-Port SRAM, 64KX72, 7.2ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, LEAD	获取价格
CYDD04S72V18-250BBC	CYPRESS	Dual-Port SRAM, 64KX72, 7.2ns, CMOS, PBGA484, 23 X 23 MM, 2.03 MM HEIGHT, 1 MM PITCH, PLAS	获取价格
CYDD09S18V18-167BBC	CYPRESS	Dual-Port SRAM, 256KX36, 9ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, MO-192, FBGA-256	获取价格
CYDD09S18V18-167BBI	CYPRESS	Dual-Port SRAM, 256KX36, 9ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, MO-192, FBGA-256	获取价格
CYDD09S18V18-167BBXC	CYPRESS	Dual-Port SRAM, 256KX36, 9ns, CMOS, PBGA256, 17 X 17 MM, 1 MM PITCH, LEAD FREE, MO-192, FB	获取价格

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