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CYD36S72V18-133BGI PDF预览

CYD36S72V18-133BGI

更新时间: 2023-01-15 00:00:00
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
52页 1093K
描述
Dual-Port SRAM, 512KX72, 13ns, CMOS, PBGA484, 27 X 27 MM, 2.33 MM HEIGHT, 1 MM PITCH, PLASTIC, BGA-484

CYD36S72V18-133BGI 数据手册

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FullFlex  
Logic Block Diagram  
The Logic Block Diagram for FullFlex72, FullFlex36, and FullFlex18 family follows: [1, 2, 3]  
FTSEL  
L
FTSEL  
CQEN  
R
CQEN  
L
R
CONFIG Block  
CONFIG Block  
PORTSTD[1:0]  
PORTSTD[1:0]  
L
R
DQ [71:0]  
R
DQ[71:0]  
L
BE [7:0]  
0
R
BE [7:0]  
R
L
CE  
CE  
0
L
CE1  
OE  
IO  
Control  
IO  
Control  
CE1  
R
L
OE  
R
L
R/  
W
R/  
W
L
R
CQ1  
L
CQ1  
CQ1  
CQ0  
R
CQ1  
CQ0  
L
R
R
L
CQ0  
CQ0  
L
R
Dual Port Array  
BUSY  
Collision Detection Logic  
BUSY  
L
R
A [20:0]  
A [20:0]  
L
R
CNT/MSK  
CNT/MSK  
L
R
ADS  
ADS  
L
R
CNTEN  
CNTEN  
L
R
Address &  
Counter Logic  
Address &  
Counter Logic  
CNTRST  
CNTRST  
L
R
RET  
RET  
R
L
CNTINT  
L
CNTINT  
R
C
C
L
R
WRP  
L
WRP  
R
TRST  
TMS  
TDI  
Mailboxes  
INT  
INT  
R
L
JTAG  
TDO  
TCK  
ZQ0  
ZQ0  
ZQ1  
R
L
ZQ1  
R
L
RESET  
LOGIC  
MRST  
READY  
READY  
L
R
LowSPD  
LowSPD  
R
L
Notes  
1. The CYD36S18V18 device has 21 address bits. The CYD36S36V18 and CYD18S18V18 devices have 20 address bits. The CYD36S72V18, CYD18S36V18, and  
CYD09S18V18 devices have 19 address bits. The CYD18S72V18, CYD09S36V18, and CYD04S18V18 devices have 18 address bits. The CYD09S72V18 and  
CYD04S36V18 devices have 17 address bits. The CYD04S72V18 and CYD02S36V18 have 16 address bits.  
2. The FullFlex72 family of devices has 72 data lines. The FullFlex36 family of devices has 36 data lines. The FullFlex18 family of devices has 18 data lines.  
3. The FullFlex72 family of devices has eight byte enables. The FullFlex36 family of devices has four byte enables. The FullFlex18 family of devices has two byte enables.  
Document Number: 38-06082 Rev. *H  
Page 2 of 52  
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