Datasheet > CY8CLED04D01

CY8CLED04D01

更新时间： 2022-12-21 13:34:38

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		驱动器
页数	文件大小	规格书
52页	1388K
描述
PowerPSoC Intelligent LED Driver

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数据手册

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CY8CLED04D01 数据手册

CY8CLED04D01, CY8CLED04D02

CY8CLED04G01, CY8CLED03D01

CY8CLED03D02, CY8CLED03G01

CY8CLED02D01, CY8CLED01D01

2. Logic Block Diagrams

Figure 2-1. CY8CLED04D0x Logic Block Diagram

SW0

CSA0

DAC0

DAC1

CSP0

Gate Drive 0

Hysteretic Mode

Controller 0

CSN0

PGND0

GD 0

External

Gate Drive 0

SW1

CSA1

DAC2

DAC3

Gate Drive 1

CSP1

Hysteretic Mode

Controller 1

CSN1

PGND1

GD 1

External

Gate Drive 1

SW2

CSA2

Gate Drive 2

DAC4

DAC5

CSP2

Hysteretic Mode

Controller 2

CSN2

PGND2

GD 2

External

Gate Drive 2

SW3

CSA3

Gate Drive 3

DAC6

DAC7

CSP3

Hysteretic Mode

Controller 3

CSN3

PGND3

GD 3

External

Gate Drive 3

FN0{0,1,2,3}

Digital Mux

4 Channel PWM/

PrISM/DMM

Analog Mux

SREGHVIN

SREGSW

Auxiliary

Power

Regulator

SREGCSP

SREGCSN

SREGFB

From Analog Mux

AINX

SREGCOMP

Global Digital Interconnect

Global Analog Interconnect

PSoC CORE

SRAM

PORT2{2}

SROM

Flash 16K

Sleep and

Watchdog

CPU Core (M8C)

Interrupt

Controller

PORT1{0,1,4,5,7}

Clock Sources

(Includes IMO and ILO)

PORT0{3,4,5,7}

DIGITAL SYSTEM

ANALOG SYSTEM

Analog Ref.

Digital

Block

Array

Analog

Block Array

Digital

Clocks

Decimator Type

POR and LVD

System Resets

Internal

Voltage Ref.

Analog

Input Muxing

2 MACs

I2C

SYSTEM RESOURCES

Document Number: 001-46319 Rev. *G

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