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CY8CLED04-68LTXIT PDF预览

CY8CLED04-68LTXIT

更新时间: 2024-01-09 03:50:26
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 显示驱动器驱动程序和接口接口集成电路控制器
页数 文件大小 规格书
37页 971K
描述
EZ-Color™ HB LED Controller

CY8CLED04-68LTXIT 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:QCCN, LCC68,.32SQ,16Reach Compliance Code:compliant
风险等级:5.75JESD-30 代码:S-PQCC-N68
端子数量:68最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:QCCN封装等效代码:LCC68,.32SQ,16
封装形状:SQUARE封装形式:CHIP CARRIER
电源:3.3/5 V认证状态:Not Qualified
子类别:Display Drivers表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:NO LEAD端子节距:0.4 mm
端子位置:QUADBase Number Matches:1

CY8CLED04-68LTXIT 数据手册

 浏览型号CY8CLED04-68LTXIT的Datasheet PDF文件第2页浏览型号CY8CLED04-68LTXIT的Datasheet PDF文件第3页浏览型号CY8CLED04-68LTXIT的Datasheet PDF文件第4页浏览型号CY8CLED04-68LTXIT的Datasheet PDF文件第6页浏览型号CY8CLED04-68LTXIT的Datasheet PDF文件第7页浏览型号CY8CLED04-68LTXIT的Datasheet PDF文件第8页 
CY8CLED04  
Figure 2. Analog System Block Diagram  
The Analog System  
All IO  
The Analog System is composed of six configurable blocks, each  
comprised of an opamp circuit allowing the creation of complex  
analog signal flows. Analog peripherals are very flexible and can  
be customized to support specific application requirements.  
Some of the more common EZ-Color analog functions (most  
available as user modules) are listed below.  
(Except Port 7)  
P0[7]  
P0[5]  
P0[6]  
P0[4]  
P0[3]  
P0[1]  
P0[2]  
P0[0]  
Analog-to-digitalconverters(upto2, with6-to14-bitresolution,  
selectable as Incremental, Delta Sigma, and SAR)  
Filters (2 and 4 pole band-pass, low-pass, and notch)  
Amplifiers (up to 2, with selectable gain to 48x)  
Instrumentation amplifiers (1 with selectable gain to 93x)  
Comparators (up to 2, with 16 selectable thresholds)  
DACs (up to 2, with 6- to 9-bit resolution)  
P2[6]  
P2[4]  
P2[3]  
P2[1]  
P2[2]  
P2[0]  
Multiplying DACs (up to 2, with 6- to 9-bit resolution)  
High current output drivers (two with 30 mA drive as a PSoC  
Core Resource)  
1.3V reference (as a System Resource)  
DTMF Dialer  
Modulators  
ACI0[1:0]  
Array Input  
ACI1[1:0]  
Correlators  
Configuration  
Peak Detectors  
Many other topologies possible  
Block  
Array  
ACB00  
ASC10  
ASD20  
ACB01  
ASD11  
ASC21  
Analog blocks are arranged in a column of three, which includes  
one CT (Continuous Time) and two SC (Switched Capacitor)  
blocks, as shown in the figure below.  
Analog Reference  
Interface to  
Digital System  
Reference  
Generators  
RefHi  
RefLo  
AGND  
AGNDIn  
RefIn  
Bandgap  
M8C Interface (Address Bus, Data Bus, Etc.)  
Document Number: 001-13108 Rev. *C  
Page 5 of 37  
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