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CY8C9540A-24PVXIT PDF预览

CY8C9540A-24PVXIT

更新时间： 2024-02-18 22:40:04
品牌 Logo 应用领域
英飞凌 - INFINEON PC光电二极管外围集成电路
页数 文件大小 规格书
32页 452K
描述
CY8C95xx

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CY8C9540A-24PVXIT 技术参数

是否Rohs认证：符合生命周期：Active
零件包装代码：SSOP包装说明：SSOP-48
针数：48Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.31.00.01
风险等级：5.76Samacsys Confidence：3
Samacsys Status：Released2D Presentation：https://componentsearchengine.com/2D/0T/985093.1.1.png
Schematic Symbol：https://componentsearchengine.com/symbol.php?partID=985093PCB Footprint：https://componentsearchengine.com/footprint.php?partID=985093
3D View：https://componentsearchengine.com/viewer/3D.php?partID=985093Samacsys PartID：985093
Samacsys Image：https://componentsearchengine.com/Images/9/CY8C9540A-24PVXIT.jpgSamacsys Thumbnail Image：https://componentsearchengine.com/Thumbnails/1/CY8C9540A-24PVXIT.jpg
Samacsys Pin Count：48Samacsys Part Category：Integrated Circuit
Samacsys Package Category：Small Outline PackagesSamacsys Footprint Name：48-pin SSOP (300mils)_inches
Samacsys Released Date：2020-06-05 04:19:38Is Samacsys：N
其他特性：IT ALSO OPERATES AT 5 VJESD-30 代码：R-PDSO-G48
JESD-609代码：e4长度：15.875 mm
湿度敏感等级：3位数：40
I/O 线路数量：40端口数量：8
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP48,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：3.3/5 V
认证状态：Not Qualified座面最大高度：2.794 mm
子类别：Parallel IO Port最大供电电压：5.25 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：7.5 mmuPs/uCs/外围集成电路类型：PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches：1

CY8C9540A-24PVXIT 数据手册

 浏览型号CY8C9540A-24PVXIT的Datasheet PDF文件第1页浏览型号CY8C9540A-24PVXIT的Datasheet PDF文件第2页浏览型号CY8C9540A-24PVXIT的Datasheet PDF文件第3页浏览型号CY8C9540A-24PVXIT的Datasheet PDF文件第5页浏览型号CY8C9540A-24PVXIT的Datasheet PDF文件第6页浏览型号CY8C9540A-24PVXIT的Datasheet PDF文件第7页 
CY8C9520A  
CY8C9540A  
CY8C9560A  
To read one or more bytes, the master device addresses the unit  
with a write cycle (= 0) to send AHI followed by ALO, readdresses  
the unit with a read cycle (= 1), and reads one or more data bytes.  
Each data byte read increments the internal address counter by  
one up to the end of the EEPROM address space. A read or write  
beyond the end of the EEPROM address space must result in a  
NAK response by the Port Expander.  
Device Access Addressing  
Following a start condition, the I2C master device sends a byte  
to address an I2C slave. This address accesses the device in the  
CY8C95xx. By default there are two possible address formats in  
binary representation: 010000A0X and 101000A0X. The first is  
used to access the multi port device and the second to access  
the EEPROM. If additional address lines (A1-A6) are used then  
the Device Addressing. Table 2 defines the device addresses.  
This addressing method uses a technique called Extendable Soft  
Addressing, described in the section Extendable Soft  
Addressing on page 9.  
To write data to the EEPROM, the master device performs one  
write cycle, with the first two bytes being AHI followed by ALO.  
This is followed by one or more data bytes. In the case of block  
writing it is advisable to set the starting address on the beginning  
of the 64-byte boundary, for example 01C0h or 0080h, but this is  
not mandatory. When a 64-byte boundary is crossed in the  
EEPROM, the I2C clock is stretched while the device performs  
an EEPROM write sequence. If the end of available EEPROM  
space is reached, then further writes are responded to with a  
NAK.  
Table 2. Device Addressing  
Multi-Port Device  
EEPROM Device  
01  
0
0
0
0
0
0
0
0
0
0
0
A
A
A
A
A
A
A
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
1
1
1
1
1
1
0
0
0
0
0
1
1
1
1
0
0
0
0
0
0
A
A
A
A
A
A
A
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
R/W  
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
A
A
1
1
1
1
1
1
1
1
1
1
1
1
Refer to Figure 6 on page 10, which illustrates memory reading  
and writing procedures for the EEPROM device.  
0
A
A
A
A
A
A
A
A
A
A
A
A
2
2
2
2
2
2
2
2
2
2
0
A
A
A
A
A
A
A
A
A
A
3
3
3
3
3
3
3
3
Multi Port I/O Device  
0
A
A
A
A
A
A
A
A
4
4
4
4
4
4
0
A
A
A
A
A
A
This device allows the user to set configurations and I/O  
operations through internal registers.  
5
5
5
5
A
6
A
A
A
6
Each data transfer is preceded by the command byte. This byte  
is used as a pointer to a register that receives or transmits data.  
Available registers are listed in Table 6 on page 11.  
When all address lines A1-A6 are used, the device being  
accessed is defined by the first byte following the address in the  
write transaction. If the most significant bit (MSb) of this byte is  
‘0’, this byte is treated as a command (register address) byte of  
the multi-port device. If the MSb is ‘1’, this byte is the first of a  
2-byte EEPROM address. In this case, the device masks the  
MSb to determine the EEPROM address.  
Serial EEPROM Device  
EEPROM reading and writing operations require 2 bytes, AHI  
and ALO, which indicate the memory address to use.  
Document Number: 38-12036 Rev. *I  
Page 4 of 32  
1234567...32

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CY8C9560A-24AXI INFINEON CY8C95xx

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