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CY8C9540A-24PVXIT

更新时间： 2024-02-29 07:46:51
品牌 Logo 应用领域
英飞凌 - INFINEON PC光电二极管外围集成电路
页数 文件大小 规格书
32页 452K
描述
CY8C95xx

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CY8C9540A-24PVXIT 技术参数

是否Rohs认证：符合生命周期：Active
零件包装代码：SSOP包装说明：SSOP-48
针数：48Reach Compliance Code：compliant
ECCN代码：EAR99HTS代码：8542.31.00.01
风险等级：5.76Samacsys Confidence：3
Samacsys Status：Released2D Presentation：https://componentsearchengine.com/2D/0T/985093.1.1.png
Schematic Symbol：https://componentsearchengine.com/symbol.php?partID=985093PCB Footprint：https://componentsearchengine.com/footprint.php?partID=985093
3D View：https://componentsearchengine.com/viewer/3D.php?partID=985093Samacsys PartID：985093
Samacsys Image：https://componentsearchengine.com/Images/9/CY8C9540A-24PVXIT.jpgSamacsys Thumbnail Image：https://componentsearchengine.com/Thumbnails/1/CY8C9540A-24PVXIT.jpg
Samacsys Pin Count：48Samacsys Part Category：Integrated Circuit
Samacsys Package Category：Small Outline PackagesSamacsys Footprint Name：48-pin SSOP (300mils)_inches
Samacsys Released Date：2020-06-05 04:19:38Is Samacsys：N
其他特性：IT ALSO OPERATES AT 5 VJESD-30 代码：R-PDSO-G48
JESD-609代码：e4长度：15.875 mm
湿度敏感等级：3位数：40
I/O 线路数量：40端口数量：8
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C封装主体材料：PLASTIC/EPOXY
封装代码：SSOP封装等效代码：SSOP48,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
峰值回流温度（摄氏度）：260电源：3.3/5 V
认证状态：Not Qualified座面最大高度：2.794 mm
子类别：Parallel IO Port最大供电电压：5.25 V
最小供电电压：3 V标称供电电压：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式：GULL WING端子节距：0.635 mm
端子位置：DUAL处于峰值回流温度下的最长时间：30
宽度：7.5 mmuPs/uCs/外围集成电路类型：PARALLEL IO PORT, GENERAL PURPOSE
Base Number Matches：1

CY8C9540A-24PVXIT 数据手册

 浏览型号CY8C9540A-24PVXIT的Datasheet PDF文件第1页浏览型号CY8C9540A-24PVXIT的Datasheet PDF文件第2页浏览型号CY8C9540A-24PVXIT的Datasheet PDF文件第4页浏览型号CY8C9540A-24PVXIT的Datasheet PDF文件第5页浏览型号CY8C9540A-24PVXIT的Datasheet PDF文件第6页浏览型号CY8C9540A-24PVXIT的Datasheet PDF文件第7页 
CY8C9520A  
CY8C9540A  
CY8C9560A  
Figure 1. Logical Structure of the I/O Port  
Architecture  
The Top Level Block Diagram on page 1 illustrates the device  
block diagram. The main blocks include the control unit, PWMs,  
EEPROM, and I/O ports. The control unit executes commands  
received from the I2C bus and transfers data between other bus  
devices and the master device.  
GPortx  
7 Drive Mode  
Registers  
The on chip EEPROM can be separated conventionally into two  
regions. The first region is designed to store data and is available  
for byte wide read/writes through the I2C bus. It is possible to  
prevent write operations by setting the WD pin to high. All  
EEPROM operations can be blocked by configuration register  
settings. The second region allows the user to store the port and  
PWM default settings using special commands. These defaults  
are automatically reloaded and processed after device power on.  
Output  
Register  
DriveMode  
Pull-Up  
Data  
DriveMode  
High Z  
PWMs  
Select PWM  
The number of I/O lines and PWM sources are listed in the  
following table.  
Interrupt  
Status  
Table 1. GPIO Availability  
Input Register  
8 Bit IO  
Port  
CY8C9520A CY8C9540A CY8C9560A  
Interrupt  
Mask  
GPort 0  
GPort 1  
GPort 2  
GPort 3  
GPort 4  
GPort 5  
GPort 6  
GPort 7  
PWMs  
8 bit  
5-8 bit[1]  
0-4 bit[1]  
8 bit  
5-8bit[1]  
0-4it[1]  
8 bit  
8 bit  
4 bit  
–
8 bit  
5-8 bit[1]  
0-4 bit[1]  
8 bit  
Pin Direction  
Inversion  
–
–
–
–
–
4
8 bit  
8 bit  
The Port Input and Output registers are separated. When the  
Output register is written, the data is sent to the external pins.  
When the Input register is read, the external pin logic levels are  
captured and transferred. As a result, the read data can be  
different from written Output register data. This enables imple-  
mentation of a quasi-bidirectional input-output mode, when the  
corresponding binary digit is configured as pulled up/down  
output.  
8 bit  
–
8 bit  
8
16  
There are four pins on GPort 2 and three on GPort 1 that can be  
used as general purpose I/O or EEPROM Write Disable (WD)  
and I2C-address input (A1-A6), depending on configuration  
settings.  
Each port has an Interrupt Mask register and an Interrupt Status  
register. Each high bit in the Interrupt Status register signals that  
there has been a change in the corresponding input line since  
the last read of that Interrupt Status register. The Interrupt Status  
register is cleared after each read. The Interrupt Mask register  
enables/disables activation of the INT line when input levels are  
changed. Each high in the Interrupt Mask register masks  
(disables) an interrupt generated from the corresponding input  
line.  
Figure 1 shows the single port logical structure. The Port Drive  
Mode register gives the option to select one of seven available  
modes for each pin separately: pulled up/down, open drain  
high/low, strong drive fast/slow, or high impedance. By default  
these configuration registers store values setting I/O pins to be  
pulled up. The Invert register enables inversion of the logic of the  
Input registers separately for each pin. The Select PWM register  
assigns pins as PWM outputs. All of these configuration registers  
are read/writable using corresponding commands in the  
multi-port device.  
Applications  
Each GPIO pin can be used to monitor and control various board  
level devices, including LEDs and system intrusion detection  
devices.  
The on board EEPROM can be used to store information such  
as error codes or board manufacturing data for read-back by  
application software for diagnostic purposes.  
Note  
1. This port contains configuration-dependant GPIO lines or A1-A6 and WD lines.  
Document Number: 38-12036 Rev. *I  
Page 3 of 32  
1234567...32

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