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CY8C28243_12 PDF预览

CY8C28243_12

更新时间: 2024-10-01 12:50:47
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
78页 2771K
描述
PSoC® Programmable System-on-Chip™

CY8C28243_12 数据手册

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CY8C28243, CY8C28403, CY8C28413  
CY8C28433, CY8C28445, CY8C28452  
CY8C28513, CY8C28533, CY8C28545  
CY8C28623, CY8C28643, CY8C28645  
PSoC® Programmable System-on-Chip™  
PSoC® Programmable System-on-Chip™  
Pull-up, pull-down, high Z, strong, or open-drain drive modes  
Features  
on all GPIOs  
Varied resource options within one PSoC® device group  
Analog input on all GPIOs  
30 mA analog outputs on GPIOs  
Configurable interrupt on all GPIOs  
Powerful Harvard-architecture processor  
M8C processor speeds up to 24 MHz  
8 × 8 Multiply, 32-bit accumulate  
Low power at high speed  
Operating voltage: 3.0 V to 5.25 V  
Operating voltages down to 1.5 V Using on-chip switched  
mode pump (SMP)  
Additional system resources  
Up to two hardware I2C resources  
• Each resource implements slave, master, or multi-master  
modes  
• Operation between 0 and 400 kHz  
Industrial temperature range: –40 °C to +85 °C  
Watchdog and Sleep timers  
User-configurable low voltage detection  
Flexible internal voltage references  
Integrated supervisory circuit  
Advanced reconfigurable peripherals (PSoC Blocks)  
Up to 12 rail-to-rail analog PSoC blocks provide:  
• Up to 14-bit ADCs  
On-chip precision voltage reference  
• Up to 9-bit DACs  
Complete development tools  
• Programmable gain amplifiers  
Free development software (PSoC Designer™)  
Full featured in-circuit emulator, and programmer  
Full speed emulation  
Flexible and functional breakpoint structure  
128 KB trace memory  
• Programmable filters and comparators  
• Multiple ADC configurations  
• Dedicated SAR ADC, up to 142 ksps with sample and hold  
• Up to 4 synchronized or independent delta-sigma ADCs for  
advanced applications  
Up to 4 limited type E analog blocks provide:  
• Dual channel capacitive sensing capability  
• Comparators with programmable DAC reference  
• Up to 10-bit single-slope ADCs  
Up to 12 digital PSoC blocks provide:  
• 8- to 32-bit timers and counters, 8- and 16-bit pulse-width  
modulators (PWMs)  
Logic Block Diagram  
Analog  
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0  
Drivers  
PSoC  
CORE  
System Bus  
• Shift register, CRC, and PRS modules  
• Up to 3 full-duplex UARTs  
Global Digital Interconnect  
Global Analog Interconnect  
SRAM  
1K  
• Up to 6 half-duplex UARTs  
• Multiple variable data length SPImasters or slaves  
• Connectable to all GPIOs  
SROM  
Flash 16K  
Sleep and  
Watchdog  
CPU Core (M8C)  
Interrupt  
Controller  
Complex peripherals by combining blocks  
Multiple Clock Sources  
(Includes IMO, ILO, PLL, and ECO)  
Precision, programmable clocking  
Internal ±2.5% 24/48 MHz main oscillator  
Optional 32.768 kHz crystal for precise on-chip clocks  
Optional external oscillator, up to 24 MHz  
Internal low speed, low power oscillator for watchdog and  
sleep functionality  
DIGITAL SYSTEM  
ANALOG SYSTEM  
Analog  
Ref.  
Analog  
Block  
Array  
Digital  
Block  
Array  
Flexible on-chip memory  
16 KB flash program storage 50,000 erase/write cycles  
1-KB SRAM data storage  
Analog  
Input  
Muxing  
In-system serial programming (ISSP)  
Partial flash updates  
Flexible protection modes  
EEPROM emulation in flash  
POR and LVD Internal Switch  
Voltage Mode  
Digital  
2
4 Type 2  
2 I2C  
Clocks MACs Decimators Blocks  
System Resets  
Ref.  
Pump  
Programmable Pin configurations  
25 mA sink, 10 mA drive on all GPIOs  
SYSTEM RESOURCES  
Cypress Semiconductor Corporation  
Document Number: 001-48111 Rev. *K  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised October 1, 2012  

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