CY8C28243, CY8C28403, CY8C28413
CY8C28433, CY8C28445, CY8C28452
CY8C28513, CY8C28533, CY8C28545
CY8C28623, CY8C28643, CY8C28645
PRELIMINARY
PSoC® Programmable System-on-Chip
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Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
Features
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Analog Input on All GPIO
30 mA Analog Outputs on GPIO
Configurable Interrupt on all GPIO
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Varied Resource Options Within One PSoC Device Group
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Powerful Harvard Architecture Processor
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M8C Processor Speeds up to 24 MHz
8x8 Multiply, 32-Bit Accumulate
Low Power at High Speed
3.0V to 5.25V Operating Voltage
Operating Voltages Down to 1.5V Using On-Chip Switched
Mode Pump (SMP)
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Additional System Resources
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Up to 2 Hardware I2C Resources
• Each Resource Implements Slave, Master, or Multi-Master
Modes
• Operation Between 0 and 400 kHz
Watchdog and Sleep Timers
User-Configurable Low Voltage Detection
Flexible Internal Voltage References
Integrated Supervisory Circuit
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Industrial Temperature Range: -40°C to +85°C
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Advanced Reconfigurable Peripherals (PSoC Blocks)
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Up to 12 Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
On-Chip Precision Voltage Reference
• Up to 9-Bit DACs
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Complete Development Tools
• Programmable Gain Amplifiers
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Free Development Software (PSoC Designer™)
Full Featured In-Circuit Emulator, and Programmer
Full Speed Emulation
Flexible and Functional Breakpoint Structure
128K Trace Memory
• Programmable Filters and Comparators
• Multiple ADC configurations
• Dedicated SAR ADC, up to 192 ksps with Sample and Hold
• Up to 4 Synchronized or Independent Delta-Sigma ADCs
for Advanced Applications
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Up to 4 Limited Type E Analog Blocks Provide:
• Dual Channel Capacitive Sensing Capability
• Comparators with Programmable DAC Reference
• Up to 10-bit Single-Slope ADCs
Up to 12 Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• Shift Register, CRC, and PRS Modules
• Up to 3 Full-Duplex UARTs
System Block Diagram
Analog
Drivers
Port 5 Port 4 Port 3 Port 2 Port 1 Port 0
PSoC
CORE
System Bus
Global Digital Interconnect
SRAM
Global Analog Interconnect
• Up to 6 Half-Duplex UARTs
• Multiple Variable Data Length SPI™ Masters or Slaves
• Connectable to All GPIO
SROM
Flash 16K
1K
Sleep and
Watchdog
CPU Core (M8C)
Interrupt
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Complex Peripherals by Combining Blocks
Controller
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Precision, Programmable Clocking
Multiple Clock Sources
(Includes IMO, ILO, PLL, and ECO)
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Internal ±2.5% 24/48 MHz Main Oscillator
Optional 32.768 kHz Crystal for Precise On-Chip Clocks
Optional External Oscillator, up to 24 MHz
Internal Low Speed, Low Power Oscillator for Watchdog and
Sleep Functionality
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref.
Analog
Block
Array
Digital
Block
Array
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Flexible On-Chip Memory
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Analog
Input
Muxing
16K Bytes Flash Program Storage 50,000 Erase/Write Cy-
cles
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1K Bytes SRAM Data Storage
In-System Serial Programming (ISSP™)
Partial Flash Updates
Flexible Protection Modes
EEPROM Emulation in Flash
POR and LVD Internal Switch
Voltage Mode
Digital
2
4 Type 2
2 I2C
Clocks MACs Decimators Blocks
System Resets
Ref.
Pump
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Programmable Pin Configurations
25 mA Sink, 10 mA Drive on All GPIO
SYSTEM RESOURCES
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Cypress Semiconductor Corporation
Document Number: 001-48111 Rev. *D
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised August 10, 2009
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