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CY8C20667-24LQXIT PDF预览

CY8C20667-24LQXIT

更新时间: 2024-01-20 19:23:22
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 传感器接近传感器控制器
页数 文件大小 规格书
43页 689K
描述
1.8 V CapSense® Controller with SmartSense™ Auto-tuning 31 Buttons, 6 Sliders, Proximity Sensors

CY8C20667-24LQXIT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFN
包装说明:HVQCCN, LCC48,.24SQ,16针数:48
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.31.00.01Factory Lead Time:1 week
风险等级:8.37位大小:8
CPU系列:M8CJESD-30 代码:S-XQCC-N48
JESD-609代码:e4长度:6 mm
湿度敏感等级:3端子数量:48
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装等效代码:LCC48,.24SQ,16封装形状:SQUARE
封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度(摄氏度):260
电源:1.8/5 V认证状态:Not Qualified
RAM(字节):2048ROM(单词):32768
ROM可编程性:FLASH座面最大高度:0.6 mm
速度:25.2 MHz子类别:Microcontrollers
最大压摆率:4 mA最大供电电压:5.5 V
最小供电电压:1.71 V标称供电电压:3.3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:NO LEAD端子节距:0.4 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:6 mmuPs/uCs/外围集成电路类型:MICROPROCESSOR CIRCUIT
Base Number Matches:1

CY8C20667-24LQXIT 数据手册

 浏览型号CY8C20667-24LQXIT的Datasheet PDF文件第1页浏览型号CY8C20667-24LQXIT的Datasheet PDF文件第2页浏览型号CY8C20667-24LQXIT的Datasheet PDF文件第3页浏览型号CY8C20667-24LQXIT的Datasheet PDF文件第5页浏览型号CY8C20667-24LQXIT的Datasheet PDF文件第6页浏览型号CY8C20667-24LQXIT的Datasheet PDF文件第7页 
CY8C20xx7/S  
®
Figure 1. CapSense System Block Diagram  
PSoC Functional Overview  
The PSoC family consists of many devices with on-chip  
controllers. These devices are designed to replace multiple  
traditional MCU-based system components with one low-cost  
single-chip programmable component. A PSoC device includes  
configurable blocks of analog and digital logic, and  
programmable interconnect. This architecture makes it possible  
for you to create customized peripheral configurations, to match  
the requirements of each individual application. Additionally, a  
fast central processing unit (CPU), flash program memory,  
SRAM data memory, and configurable I/O are included in a  
range of convenient pinouts.  
CS1  
CS2  
IDAC  
CSN  
Vr  
The architecture for this device family, as shown in the Logic  
Block Diagram on page 2, consists of three main areas:  
Reference  
Buffer  
The core  
Cexternal (P0[1]  
or P0[3])  
Comparator  
CapSense analog system  
System resources  
Mux  
Mux  
Refs  
A common, versatile bus allows connection between I/O and the  
analog system.  
Each CY8C20x37/47/67/S PSoC device includes a dedicated  
CapSense block that provides sensing and scanning control  
circuitry for capacitive sensing applications. Depending on the  
PSoC package, up to 34 GPIOs are also included. The GPIOs  
provide access to the MCU and analog mux.  
Cap Sense Counters  
CSCLK  
PSoC Core  
CapSense  
Clock Select  
IMO  
Oscillator  
The PSoC core is a powerful engine that supports a rich  
instruction set. It encompasses SRAM for data storage, an  
interrupt controller, sleep and watchdog timers, and IMO and  
ILO. The CPU core, called the M8C, is a powerful processor with  
speeds up to 24 MHz. The M8C is a 4-million instructions per  
second (MIPS), 8-bit Harvard-architecture microprocessor.  
Analog Multiplexer System  
The analog mux bus can connect to every GPIO pin. Pins are  
connected to the bus individually or in any combination. The bus  
also connects to the analog system for analysis with the  
CapSense block comparator.  
CapSense System  
The analog system contains the capacitive sensing hardware.  
Several hardware algorithms are supported. This hardware  
performs capacitive sensing and scanning without requiring  
external components. The analog system is composed of the  
CapSense PSoC block and an internal 1 V or 1.2 V analog  
reference, which together support capacitive sensing of up to 31  
inputs[3]. Capacitive sensing is configurable on each GPIO pin.  
Scanning of enabled CapSense pins is completed quickly and  
easily across multiple ports.  
Switch-control logic enables selected pins to precharge  
continuously under hardware control. This enables capacitive  
measurement for applications such as touch sensing. Other  
multiplexer applications include:  
Complex capacitive sensing interfaces, such as sliders and  
touchpads.  
Chip-wide mux that allows analog input from any I/O pin.  
Crosspoint connection between any I/O pin combinations.  
SmartSenseAuto-tuning  
SmartSense auto-tuning is an innovative solution from Cypress  
that removes manual tuning of CapSense applications. This  
solution is easy to use and provides robust noise immunity. It is  
the only auto-tuning solution that establishes, monitors, and  
maintains all required tuning parameters of each sensor during  
run time. SmartSense auto-tuning allows engineers to go from  
prototyping to mass production without retuning for  
manufacturing variations in PCB and/or overlay material  
properties.  
Note  
3. 34 GPIOs = 31 pins for capacitive sensing+2 pins for I2C + 1 pin for modulator capacitor.  
Document Number: 001-69257 Rev. *I  
Page 4 of 43  

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