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CY7C960-UM

更新时间： 2024-01-23 22:48:53

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		控制器
页数	文件大小	规格书
10页	252K
描述
Low Cost VMEbus Interface Controller Family

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技术参数
数据手册

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CY7C960-UM 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
零件包装代码：	QFP	包装说明：	14 X 14 MM, CAVITY-UP, CERAMIC, TQFP-64
针数：	64	Reach Compliance Code：	not_compliant
风险等级：	5.89	Is Samacsys：	N
地址总线宽度：		最大数据传输速率：	80 MBps
外部数据总线宽度：		JESD-30 代码：	S-CQFP-G64
JESD-609代码：	e0	长度：	14 mm
湿度敏感等级：	3	端子数量：	64
最高工作温度：	125 °C	最低工作温度：	-55 °C
封装主体材料：	CERAMIC, METAL-SEALED COFIRED	封装代码：	QFP
封装等效代码：	QFP64,.66SQ,32	封装形状：	SQUARE
封装形式：	FLATPACK	峰值回流温度（摄氏度）：	225
电源：	5 V	认证状态：	Not Qualified
筛选级别：	38535Q/M;38534H;883B	座面最大高度：	3 mm
子类别：	Bus Controllers	最大压摆率：	100 mA
标称供电电压：	5 V	表面贴装：	YES
技术：	MOS	温度等级：	MILITARY
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	GULL WING
端子节距：	0.8 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	30	宽度：	14 mm
uPs/uCs/外围集成电路类型：	BUS CONTROLLER, VME	Base Number Matches：	1

CY7C960-UM 数据手册

CY7C960

CY7C961

To assist in generating the configuration file, a Win-

dows™-based program is available which guides the user through

the process of selecting appropriate options. Contact your Sales

Office for further details.

The CY7C961 master block facility provides “block transfer on

demand” capability for slave cards built around the Cypress

CY7C961/CY7C964 chipset. This facility allows one or many

VMEbus masters to write short series of commands to the

slave card, telling it how much data to move, where to get it

from, where to put it, and what transfer protocol to use while

moving it. Blocks can be moved over the VMEbus as indivisible

single cycles or BLTs. The protocol menu includes D8, D16,

D32, MD32, or D64. A16, A24, A32, A40, and A64 address

spaces can be specified. Burst lengths from 16 bytes to 8

megabytes can be requested. Eight registers accessible from

the VMEbus make the facility simple to configure and simple

to control. The facility has a busy semaphore, a VMEbus Inter-

rupt on completion feature with a programmable Status/ID

byte, and a built in requester and bus grant daisychain.

The CY7C961 is a true superset of the CY7C960. Signal pins

have been added to control CY7C964 DMA functions. Existing

VMEbus input pins have been changed to bidirectional and

augmented to complete a master interface. A data port and

chip select signal (SELECTLM*) complete the pin additions.

As a VMEbus Slave, the CY7C961 behaves in every respect

like the CY7C960. It simply has more pins, a master block

transfer facility, and (because of the addition of the BBSY* con-

nection) full lock cycle support.

From a system perspective, the CY7C961 master block trans-

fer capability can be viewed as a DMA channel that resides on

the slave card, but is controlled over the VMEbus by one or

more VMEbus masters or programmed from the local bus.

System Diagram Using the CY7C960

LA[31:0]

DRAMMEMORY

DBE[3:0], RW

I/O

LACK*

RAS*, CAS*, ROW,COL

LIRQ*

CS[2:0]

SWDEN

SWAP

BUFFER

DECODER

VCOMP

LA [31:0]

REGION

LA [7:1, LWORD]

CY7C964

CY7C960

D[31:0]

VMEDATABUS

VME ADDRESS BUS

A [31:1], LWORD*

VMEINTERRUPT BUS

c960–5

1 2 345 6 7...10

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与CY7C960-UM相关器件

型号	品牌	描述	获取价格	数据表
CY7C960-UMB	CYPRESS	Low Cost VMEbus Interface Controller Family	获取价格
CY7C961	CYPRESS	Low Cost VMEbus Interface Controller Family	获取价格
CY7C961-AC	ETC	VME/VMS/VXI/VSB Bus Interface/Controller	获取价格
CY7C961-NC	CYPRESS	Low Cost VMEbus Interface Controller Family	获取价格
CY7C964	CYPRESS	Bus Interface Logic Circuit	获取价格
CY7C964A	CYPRESS	Bus Interface Logic Circuit	获取价格

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