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CY7C460A-25PTC

更新时间： 2024-09-23 22:36:27
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 先进先出芯片
页数 文件大小 规格书
15页 253K
描述
Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs

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中文翻译

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CY7C460A-25PTC 技术参数

生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP28,.3针数：28
Reach Compliance Code：unknownECCN代码：EAR99
HTS代码：8542.32.00.71风险等级：5.31
最长访问时间：25 ns其他特性：RETRANSMIT
最大时钟频率 (fCLK)：50 MHz周期时间：35 ns
JESD-30 代码：R-PDIP-T28长度：35.4965 mm
内存密度：73728 bit内存集成电路类型：OTHER FIFO
内存宽度：9功能数量：1
端子数量：28字数：8192 words
字数代码：8000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：8KX9输出特性：3-STATE
可输出：NO封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装等效代码：DIP28,.3
封装形状：RECTANGULAR封装形式：IN-LINE
并行/串行：PARALLEL电源：5 V
认证状态：Not Qualified座面最大高度：4.826 mm
最大待机电流：0.008 A子类别：FIFOs
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：COMMERCIAL
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL宽度：7.62 mm
Base Number Matches：1

CY7C460A-25PTC 数据手册

 浏览型号CY7C460A-25PTC的Datasheet PDF文件第2页浏览型号CY7C460A-25PTC的Datasheet PDF文件第3页浏览型号CY7C460A-25PTC的Datasheet PDF文件第4页浏览型号CY7C460A-25PTC的Datasheet PDF文件第5页浏览型号CY7C460A-25PTC的Datasheet PDF文件第6页浏览型号CY7C460A-25PTC的Datasheet PDF文件第7页 
60A  
CY7C460A/CY7C462A  
CY7C464A/CY7C466A  
Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs  
Features  
Functional Description  
• High-speed, low-power, first-in first-out (FIFO)  
memories  
• 8K x 9 FIFO (CY7C460A)  
• 16K x 9 FIFO (CY7C462A)  
• 32K x 9 FIFO (CY7C464A)  
• 64K x 9 FIFO (CY7C466A)  
• 10-ns access times, 20-ns read/write cycle times  
• High-speed 50-MHz read/write independent of  
depth/width  
• Low operating power  
— ICC= 60 mA  
The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are  
respectively, 8K, 16K, 32K, and 64K words by 9-bit wide first-in  
first-out (FIFO) memories. Each FIFO memory is organized  
such that the data is read in the same sequential order that it  
was written. Full and Empty flags are provided to prevent over-  
run and underrun. Three additional pins are also provided to  
facilitate unlimited expansion in width, depth, or both. The  
depth expansion technique steers the control signals from one  
device to another by passing tokens.  
The read and write operations may be asynchronous; each  
can occur at a rate of up to 50 MHz. The write operation occurs  
when the Write (W) signal is LOW. Read occurs when Read  
(R) goes LOW. The nine data outputs go to the high-imped-  
ance state when R is HIGH.  
— ISB =8 mA  
• Asynchronous read/write  
• Empty and Full flags  
• Half Full flag (in standalone mode)  
• Retransmit (in standalone mode)  
• TTL-compatible  
A Half Full (HF) output flag is provided that is valid in the stan-  
dalone (single device) and width expansion configurations. In  
the depth expansion configuration, this pin provides the ex-  
pansion out (XO) information that is used to tell the next FIFO  
that it will be activated.  
• Width and Depth Expansion Capability  
• 5V ± 10% supply  
• PLCC, LCC, 300-mil and 600-mil DIP packaging  
• Three-state outputs  
• Pin compatible density upgrade to CY7C42X/46X family  
• Pin compatible and functionally equivalent to IDT7205,  
IDT7206, IDT7207, IDT7208  
In the standalone and width expansion configurations, a LOW  
on the Retransmit (RT) input causes the FIFOs to retransmit  
the data. Read Enable (R) and Write Enable (W) must both be  
HIGH during a retransmit cycle, and then R is used to access  
the data.  
The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are  
fabricated using Cypress’s advanced 0.5µ RAM3 CMOS tech-  
nology. Input ESD protection is greater than 2000V and  
latch-up is prevented by careful layout and the use of guard  
rings.  
Pin Configurations  
LogicBlockDiagram  
DATAINPUTS  
DIP  
Top View  
(D −D  
)
PLCC/LCC  
Top View  
0
8
1
28  
V
CC  
W
2
3
4
27  
26  
D
D
4
WRITE  
CONTROL  
8
4
3
2
1
32 31 30  
29  
W
D
2
D
D
5
6
7
6
D
D
5
3
DUAL PORT  
RAM ARRAY  
8K x 9  
16K x 9  
32K x 9  
64K x 9  
D
D
28  
27  
7
1
D
25  
24  
23  
22  
21  
D
6
2
WRITE  
POINTER  
READ  
POINTER  
NC  
0
5
D
D
1
7
7C460A  
7C462A  
7C464A  
7C466A  
7C460A  
7C462A  
7C464A  
7C466A  
XI  
FL/RT  
MR  
8
9
26  
25  
24  
23  
6
D
FL/RT  
MR  
EF  
0
FF  
7
XI  
FF  
Q
0
EF  
10  
11  
8
Q
1
XO/HF  
Q
9
20  
19  
18  
17  
16  
15  
0
XO/HF  
THREE–  
NC  
Q
7
6
12  
13  
22  
21  
10  
11  
12  
13  
Q
1
Q
STATE  
7
Q
2
Q
BUFFERS  
Q
6
Q
2
14 15 16 17 18 19 20  
Q
3
Q
8
Q
5
DATAOUTPUTS  
Q
4
(Q -Q  
0
)
8
14  
R
GND  
MR  
FL/RT  
RESET  
LOGIC  
C46XA–2  
READ  
CONTROL  
R
C46XA–3  
FLAG  
LOGIC  
EF  
FF  
EXPANSION  
LOGIC  
XI  
XO/HF  
C46XA–1  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
Document #: 38-06011 Rev. *A  
Revised December 26, 2002  
1234567...15

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