5秒后页面跳转
捷配首页

Datasheet > CY7C462-15JC
CY7C462-15JC PDF预览

CY7C462-15JC

更新时间： 2024-09-23 23:45:51
品牌 Logo 应用领域
其他 - ETC 内存集成电路先进先出芯片时钟
页数 文件大小 规格书
14页 239K
描述
IC-SM 16KX9 CMOS FIFO

阅读下载

中文翻译

获取价格

CY7C462-15JC 数据手册

 浏览型号CY7C462-15JC的Datasheet PDF文件第2页浏览型号CY7C462-15JC的Datasheet PDF文件第3页浏览型号CY7C462-15JC的Datasheet PDF文件第4页浏览型号CY7C462-15JC的Datasheet PDF文件第5页浏览型号CY7C462-15JC的Datasheet PDF文件第6页浏览型号CY7C462-15JC的Datasheet PDF文件第7页 
CY7C460A/CY7C462A  
CY7C464A/CY7C466A  
Asynchronous, Cascadable 8K/16K/32K/64K x9 FIFOs  
Features  
Functional Description  
• High-speed, low-power, first-in first-out (FIFO)  
memories  
• 8K x 9 FIFO (CY7C460A)  
• 16K x 9 FIFO (CY7C462A)  
• 32K x 9 FIFO (CY7C464A)  
• 64K x 9 FIFO (CY7C466A)  
• 10-ns access times, 20-ns read/write cycle times  
• High-speed 50-MHz read/write independent of  
depth/width  
• Low operating power  
The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are  
respectively, 8K, 16K, 32K, and 64K words by 9-bit wide first-in  
first-out (FIFO) memories. Each FIFO memory is organized  
such that the data is read in the same sequential order that it  
was written. Full and Empty flags are provided to prevent over-  
run and underrun. Three additional pins are also provided to  
facilitate unlimited expansion in width, depth, or both. The  
depth expansion technique steers the control signals from one  
device to another by passing tokens.  
The read and write operations may be asynchronous; each  
can occur at a rate of up to 50 MHz. The write operation occurs  
when the Write (W) signal is LOW. Read occurs when Read  
(R) goes LOW. The nine data outputs go to the high-imped-  
ance state when R is HIGH.  
— I = 60 mA  
CC  
— I =8 mA  
SB  
• Asynchronous read/write  
• Empty and Full flags  
• Half Full flag (in standalone mode)  
• Retransmit (in standalone mode)  
• TTL-compatible  
A Half Full (HF) output flag is provided that is valid in the stan-  
dalone (single device) and width expansion configurations. In  
the depth expansion configuration, this pin provides the expan-  
sion out (XO) information that is used to tell the next FIFO that  
it will be activated.  
• Width and Depth Expansion Capability  
In the standalone and width expansion configurations, a LOW  
on the Retransmit (RT) input causes the FIFOs to retransmit  
the data. Read Enable (R) and Write Enable (W) must both be  
HIGH during a retransmit cycle, and then R is used to access  
the data.  
5V 10% supply  
•
±
• PLCC, LCC, 300-mil and 600-mil DIP packaging  
• Three-state outputs  
• Pin compatible density upgrade to CY7C42X/46X family  
• Pin compatible and functionally equivalent to IDT7205,  
IDT7206, IDT7207, IDT7208  
The CY7C460A, CY7C462A, CY7C464A, and CY7C466A are  
fabricated using Cypress’s advanced 0.5µ RAM3 CMOS tech-  
nology. Input ESD protection is greater than 2000V and  
latch-up is prevented by careful layout and the use of guard  
rings.  
Pin Configurations  
Logic BlockDiagram  
DATAINPUTS  
DIP  
Top View  
(D −D  
)
PLCC/LCC  
Top View  
0
8
1
28  
V
CC  
W
2
3
4
27  
26  
D
D
4
WRITE  
CONTROL  
8
4
3
2
1
32 31 30  
29  
W
D
2
D
D
5
6
7
6
D
D
5
3
DUAL PORT  
RAM ARRAY  
8K x 9  
16K x 9  
32K x 9  
64K x 9  
D
D
28  
27  
7
1
D
25  
24  
23  
22  
21  
D
6
2
WRITE  
POINTER  
READ  
POINTER  
NC  
0
5
D
D
1
7
7C460A  
7C462A  
7C464A  
7C466A  
7C460A  
7C462A  
7C464A  
7C466A  
XI  
FL/RT  
MR  
8
9
26  
25  
24  
23  
D
0
XI  
FF  
6
FL/RT  
MR  
EF  
FF  
7
Q
0
EF  
10  
11  
8
Q
1
XO/HF  
Q
9
20  
19  
18  
17  
16  
15  
0
XO/HF  
THREE–  
NC  
Q
7
6
12  
13  
22  
21  
Q
1
10  
11  
12  
13  
Q
STATE  
7
Q
2
Q
BUFFERS  
Q
6
Q
2
14 15 16 17 18 19 20  
Q
3
Q
8
Q
5
DATAOUTPUTS  
Q
4
(Q -Q  
0
)
8
14  
R
GND  
MR  
FL/RT  
RESET  
LOGIC  
C46XA–2  
READ  
CONTROL  
R
C46XA–3  
FLAG  
LOGIC  
EF  
FF  
EXPANSION  
LOGIC  
XI  
XO/HF  
C46XA–1  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
October 4, 1999  
1234567...14

中文翻译

下载PDF

与CY7C462-15JC相关器件

型号 品牌 获取价格 描述 数据表
CY7C462-15JCR CYPRESS

获取价格

 		FIFO, 16KX9, 15ns, Asynchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C462-15JCT CYPRESS

获取价格

 		FIFO, 16KX9, 15ns, Asynchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C462-15LC ETC

获取价格

 		x9 Asynchronous FIFO
CY7C462-15LMB CYPRESS

获取价格

 		FIFO, 16KX9, 15ns, Asynchronous, CMOS, CQCC32, LCC-32
CY7C462-20LMB ETC

获取价格

 		x9 Asynchronous FIFO
CY7C462-25DC ETC

获取价格

 		x9 Asynchronous FIFO
CY7C462-25JCR CYPRESS

获取价格

 		FIFO, 16KX9, 25ns, Asynchronous, CMOS, PQCC32, PLASTIC, LCC-32
CY7C462-25LC ETC

获取价格

 		x9 Asynchronous FIFO
CY7C462-25PI ETC

获取价格

 		x9 Asynchronous FIFO
CY7C462-40DC ETC

获取价格

 		x9 Asynchronous FIFO

与CY7C462-15JC相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证