Datasheet > 存储 > FIFO> CY7C4261V-15JCR

CY7C4261V-15JCR

更新时间： 2024-02-01 08:52:38

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		先进先出芯片
页数	文件大小	规格书
16页	455K
描述
FIFO, 16KX9, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32

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技术参数
数据手册

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CY7C4261V-15JCR 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFJ
包装说明：	QCCJ, LDCC32,.5X.6	针数：	32
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.32.00.71	Factory Lead Time：	1 week
风险等级：	8.52	最长访问时间：	10 ns
最大时钟频率 (fCLK)：	66.7 MHz	周期时间：	15 ns
JESD-30 代码：	R-PQCC-J32	JESD-609代码：	e3
长度：	13.97 mm	内存密度：	147456 bit
内存集成电路类型：	OTHER FIFO	内存宽度：	9
湿度敏感等级：	3	功能数量：	1
端子数量：	32	字数：	16384 words
字数代码：	16000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	16KX9	输出特性：	3-STATE
可输出：	YES	封装主体材料：	PLASTIC/EPOXY
封装代码：	QCCJ	封装等效代码：	LDCC32,.5X.6
封装形状：	RECTANGULAR	封装形式：	CHIP CARRIER
并行/串行：	PARALLEL	峰值回流温度（摄氏度）：	260
电源：	3.3 V	认证状态：	Not Qualified
座面最大高度：	3.556 mm	最大待机电流：	0.004 A
子类别：	FIFOs	最大压摆率：	0.025 mA
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Matte Tin (Sn)	端子形式：	J BEND
端子节距：	1.27 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	20	宽度：	11.43 mm
Base Number Matches：	1

CY7C4261V-15JCR 数据手册

CY7C4281V/CY7C4291V CY7C4261V/CY7C4271V16K/32K/64K/128K

x 9 Low-Voltage Deep Sync™ FIFOs

CY7C4261V/CY7C4271V

CY7C4281V/CY7C4291V

16K/32K/64K/128K x 9 Low-Voltage Deep Sync™ FIFOs

• Pin-compatible density upgrade to CY7C42X1V family

Features

• Pb-Free Packages Available

• 3.3V operation for low power consumption and easy

integration into low-voltage systems

Functional Description

• High-speed, low-power, first-in first-out (FIFO)

memories

The CY7C4261/71/81/91V are high-speed, low-power FIFO

memories with clocked read and write interfaces. All are nine

bits wide. The CY7C4261/71/81/91V are pin-compatible to the

CY7C42x1V Synchronous FIFO family. Programmable

features include Almost Full/Almost Empty flags. These FIFOs

provide solutions for a wide variety of data buffering needs,

including high-speed data acquisition, multiprocessor inter-

faces, and communications buffering.

• 16K × 9 (CY7C4261V)

• 32K × 9 (CY7C4271V)

• 64K × 9 (CY7C4281V)

• 128K × 9 (CY7C4291V)

• 0.35-micron CMOS for optimum speed/power

These FIFOs have 9-bit input and output ports that are

controlled by separate clock and enable signals. The input port

is controlled by a free-running clock (WCLK) and two

write-enable pins (WEN1, WEN2/LD).

• High-speed 100-MHz operation (10-ns read/write cycle

times)

• Low power

— I_CC= 25 mA

— I_SB= 4 mA

When WEN1 is LOW and WEN2/LD is HIGH, data is written

into the FIFO on the rising edge of the WCLK signal. While

WEN1 and WEN2/LD are held active, data is continually

written into the FIFO on each WCLK cycle. The output port is

controlled in a similar manner by a free-running read clock

(RCLK) and two read enable pins (REN1, REN2). In addition,

the CY7C4261/71/81/91V has an output enable pin (OE). The

read (RCLK) and write (WCLK) clocks may be tied together for

single-clock operation or the two clocks may be run indepen-

dently for asynchronous read/write applications. Clock

frequencies up to 100 MHz are achievable. Depth expansion

is possible using one enable input for system control, while the

other enable is controlled by expansion logic to direct the flow

of data.

• Fully asynchronous and simultaneous read and write

operation

• Empty, Full, and programmable Almost Empty and

Almost Full status flags

• Output Enable (OE) pin

• Independent read and write enable pins

• Supports free-running 50% duty cycle clock inputs

• Width- Expansion capability

• Pin-compatible 3.3V solutions for CY7C4261/71/81/91

D_0–8

LogicBlock Diagram

Pin Configuration

PLCC

Top View

INPUT

32 31 30

WCLK

WEN1WEN2/LD

PAF

PAE

FLAG

WEN1

WCLK

WEN2/LD

PROGRAM

CY7C4261V

CY7C4271V

CY7C4281V

CY7C4291V

WRITE

GND

REN1

RCLK

REN2

CONTROL

PAE

PAF

FLAG

LOGIC

Dual Port

RAM Array

16K/32K

14 15 16 17 18 19 20

WRITE

POINTER

READ

64K/128K

x 9

POINTER

RESET

LOGIC

THREE-STATE

READ

CONTROL

OUTPUT

Q_0–8

RCLK

REN1 REN2

Cypress Semiconductor Corporation

Document #: 38-06013 Rev. *B

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised August 2, 2005

12 3 4 5 6 7...16

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与CY7C4261V-15JCR相关器件

型号	品牌	描述	获取价格	数据表
CY7C4261V-15JI	CYPRESS	16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs	获取价格
CY7C4261V-15JIR	CYPRESS	FIFO, 16KX9, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32	获取价格
CY7C4261V-15JIT	CYPRESS	FIFO, 16KX9, 10ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32	获取价格
CY7C4261V-15JXC	CYPRESS	16K/32K/64K/128K x 9 Low-Voltage Deep Sync⑩ F	获取价格
CY7C4261V-25JC	CYPRESS	16K/32K/64K/128K x 9 Low-Voltage Deep Sync FIFOs	获取价格
CY7C4261V-25JCR	CYPRESS	FIFO, 16KX9, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32	获取价格

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