16K/32K
x 9 Deep Sync FIFOsCY7C4271CY7C4261
CY7C4261
CY7C4271
16K/32K x 9 Deep Sync FIFOs
• Pb-Free Packages Available
Features
Functional Description
• High-speed, low-power, first-in first-out (FIFO)
memories
The CY7C4261/71 are high-speed, low-power FIFO
memories with clocked read and write interfaces. All are nine
bits wide. The CY7C4261/71 are pin-compatible to the
CY7C42X1 Synchronous FIFO family. The CY7C4261/71 can
be cascaded to increase FIFO width. Programmable features
include Almost Full/Almost Empty flags. These FIFOs provide
solutions for a wide variety of data buffering needs, including
high-speed data acquisition, multiprocessor interfaces, and
communications buffering.
• 16K × 9 (CY7C4261)
• 32K × 9 (CY7C4271)
• 0.5-micron CMOS for optimum speed/power
• High-speed 100-MHz operation (10-ns read/write cycle
times)
• Low power — ICC = 35 mA
• Fully asynchronous and simultaneous read and write
operation
These FIFOs have 9-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and two
write-enable pins (WEN1, WEN2/LD).
• Empty, Full, HalfFull, andprogrammableAlmostEmpty
and Almost Full status flags
• TTL-compatible
When WEN1 is LOW and WEN2/LD is HIGH, data is written
into the FIFO on the rising edge of the WCLK signal. While
WEN1, WEN2/LD is held active, data is continually written into
the FIFO on each WCLK cycle. The output port is controlled in
a similar manner by a free-running read clock (RCLK) and two
read enable pins (REN1, REN2). In addition, the CY7C4261/71
has an output enable pin (OE). The read (RCLK) and write
(WCLK) clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read/write applications. Clock frequencies up to 100 MHz are
achievable. Depth expansion is possible using one enable
input for system control, while the other enable is controlled by
expansion logic to direct the flow of data.
• Output Enable (OE) pins
• Independent read and write enable pins
• Center power and ground pins for reduced noise
• Supports free-running 50% duty cycle clock inputs
• Width-Expansion Capability
• Military temp SMD Offering – CY7C4271-15LMB
• 32-pin PLCC/LCC and 32-pin TQFP
• Pin-compatible density upgrade to CY7C42X1 family
• Pin-compatible density upgrade to
IDT72201/11/21/31/41/51
PLCC/LCC
Top View
D
Logic Block Diagram
0–8
Pin Configuration
INPUT
REGISTER
4
3
2
1
32 31 30
29
D
RS
1
5
6
7
D
28
27
26
0
WEN1
WCLK
WEN2/LD
PAF
PAE
WCLK WEN1 WEN2/LD
8
9
CY7C4261
CY7C4271
GND
FLAG
PROGRAM
REGISTER
V
CC
25
24
23
22
21
REN1
RCLK
REN2
OE
Q
8
10
11
12
13
Q
7
Q
6
Q
5
WRITE
CONTROL
EF
14 15 16 17 18 19 20
PAE
PAF
FF
FLAG
LOGIC
TQFP
RAM
Top View
ARRAY
16Kx 9
32Kx 9
WRITE
POINTER
READ
POINTER
32 31 30 29 28 27 26 25
1
2
3
4
5
6
7
8
24
WEN1
D
1
D
0
RESET
LOGIC
23
WCLK
RS
WEN2/LD
22
21
20
19
PAF
PAE
CY7C4261
CY7C4271
V
CC
THREE-STATE
OUTPUT REGISTER
Q
8
GND
REN1
READ
CONTROL
Q
7
Q
6
RCLK
REN2
18
17
OE
Q
5
Q
9
10 11 12 13 14 15 16
0–8
RCLK REN1 REN2
Cypress Semiconductor Corporation
Document #: 38-06015 Rev. *C
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Revised August 2, 2005
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