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CY7C4251V-15JCT PDF预览

CY7C4251V-15JCT

更新时间： 2023-08-15 00:00:00
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 先进先出芯片
页数 文件大小 规格书
18页 525K
描述
FIFO, 8KX9, 11ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32

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CY7C4251V-15JCT 数据手册

 浏览型号CY7C4251V-15JCT的Datasheet PDF文件第1页浏览型号CY7C4251V-15JCT的Datasheet PDF文件第2页浏览型号CY7C4251V-15JCT的Datasheet PDF文件第3页浏览型号CY7C4251V-15JCT的Datasheet PDF文件第5页浏览型号CY7C4251V-15JCT的Datasheet PDF文件第6页浏览型号CY7C4251V-15JCT的Datasheet PDF文件第7页 
CY7C4421V/4201V/4211V/4221V  
CY7C4231V/4241V/4251V  
64 x 9  
6
256 x 9  
7
512 x 9  
1K x 9  
7
0
0
0
0
0
0
0
0
0
0
8
8
8
8
8
8
8
8
8
8
8
8
7
8
8
8
8
Empty Offset (LSB) Reg.  
Default Value = 007h  
Empty Offset (LSB) Reg.  
Default Value = 007h  
Empty Offset (LSB) Reg.  
Default Value = 007h  
Empty Offset (LSB) Reg.  
Default Value = 007h  
0
0
0
0
1
(MSB)  
(MSB)  
00  
0
0
6
7
7
7
Full Offset (LSB) Reg  
Default Value = 007h  
Full Offset (LSB) Reg  
Default Value = 007h  
Full Offset (LSB) Reg  
Default Value = 007h  
Full Offset (LSB) Reg  
Default Value = 007h  
0
1
(MSB)  
0
(MSB)  
00  
2K x 9  
4K x 9  
8K x 9  
0
0
0
0
0
0
0
0
0
8
8
8
8
7
8
8
8
8
7
8
8
8
8
7
Empty Offset (LSB) Reg.  
Default Value = 007h  
Empty Offset (LSB) Reg.  
Default Value= 007h  
Empty Offset (LSB) Reg.  
Default Value = 007h  
0
0
0
2
3
4
(MSB)  
0000  
(MSB)  
00000  
(MSB)  
000  
7
7
7
Full Offset (LSB) Reg  
Default Value = 007h  
Full Offset (LSB) Reg  
Default Value= 007h  
Full Offset (LSB) Reg  
Default Value = 007h  
2
3
4
(MSB)  
000  
(MSB)  
0000  
(MSB)  
00000  
Figure 1. Offset Register Location and Default Values  
Programmable Flag (PAE, PAF) Operation  
The number formed by the empty offset least significant bit  
register and empty offset most significant register is referred  
to as n and determines the operation of PAE. PAE is synchro-  
nized to the LOW-to-HIGH transition of RCLK by one flip-flop  
and is LOW when the FIFO contains n or fewer unread words.  
PAE is set HIGH by the LOW-to-HIGH transition of RCLK  
when the FIFO contains (n+1) or greater unread words.  
Whether the flag offset registers are programmed as  
described in Table 1 or the default values are used, the  
programmable Almost Empty Flag (PAE) and programmable  
Almost Full Flag (PAF) states are determined by their corre-  
sponding offset registers and the difference between the read  
and write pointers.  
The number formed by the full offset least significant bit  
register and full offset most significant bit register is referred to  
as m and determines the operation of PAF. PAE is synchro-  
nized to the LOW-to-HIGH transition of WCLK by one flip-flop  
and is set LOW when the number of unread words in the FIFO  
is greater than or equal to CY7C4421V (64 – m), CY7C4201V  
(256 – m), CY7C4211V (512 – m), CY7C4221V (1K – m),  
Table 1. Writing the Offset Registers  
LD WEN  
WCLK[1]  
Selection  
0
0
Empty Offset (LSB)  
Empty Offset (MSB)  
Full Offset (LSB)  
Full Offset (MSB)  
CY7C4231V (2K  
– m), CY7C4241V (4K – m), and  
CY7C4251V (8K – m). PAF is set HIGH by the LOW-to-HIGH  
transition of WCLK when the number of available memory  
locations is greater than m.  
0
1
1
0
1
No Operation  
Write Into FIFO  
No Operation  
1
Note:  
1. The same selection sequence applies to reading from the registers. REN1 and REN2 are enabled and a read is performed on the LOW-to-HIGH transition of RCLK.  
Document #: 38-06010 Rev. *B  
Page 4 of 18  
1234567...18

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与CY7C4251V-15JCT相关器件

型号 品牌 描述 获取价格 数据表
CY7C4251V-25AC CYPRESS Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

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CY7C4251V-25AXC CYPRESS Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs

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CY7C4251V-25JC CYPRESS FIFO, 8KX9, 15ns, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32

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CY7C4251V-25JCR CYPRESS FIFO, 8KX9, Synchronous, CMOS, PQCC32, PLASTIC, LCC-32

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CY7C4251V-25JCT CYPRESS 暂无描述

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CY7C4251V-35AC CYPRESS FIFO, 8KX9, 20ns, Synchronous, CMOS, PQFP32, 7 X 7 MM, 1 MM HEIGHT, PLASTIC, TQFP-32

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