CY7C4205/CY7C4215
CY7C4225/CY7C4245
Selection Guide
Description
-10
-15
Maximum frequency (MHz)
Maximum access time (ns)
Minimum cycle time (ns)
100
8
66.7
10
15
4
10
3
Minimum data or enable set-up (ns)
Minimum data or enable hold (ns)
Maximum flag delay (ns)
0.5
8
1
10
45
50
Operating current (ICC2) (mA) @ 20MHz
Commercial
Industrial
45
50
Parameter
Density
CY7C4205
CY7C4215
CY7C4225
CY7C4245
256 x 18
512 x 18
1K x 18
4K x 18
Packages
64-pin TQFP
(14 x 14, 10 x 10)
64-pin TQFP
(14 x 14, 10 x 10)
64-pin TQFP
(14 x 14, 10 x 10)
64-pin TQFP
(14 x 14, 10 x 10)
Pin Definitions
Signal Name
Description
Data inputs
IO
I
Function
D017
Q017
WEN
REN
Data inputs for an 18-bit bus.
Data outputs
Write enable
Read enable
Write clock
O
I
Data outputs for an 18-bit bus.
Enables the WCLK input.
Enables the RCLK input.
I
WCLK
I
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full.
When LD is asserted, WCLK writes data into the programmable flag-offset register.
RCLK
Read clock
I
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-offset
register.
WXO/HF
Write expansion
out/half full flag
O
Dual-mode pin. Single device or width expansion - Half Full status flag. Cascaded – Write
Expansion Out signal, connected to WXI of next device.
EF
Empty flag
Full flag
O
O
O
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
FF
PAE
Programmable
almost empty
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO. PAE is asynchronous when VCC/SMODE is tied to VCC
;
it is synchronized to RCLK when VCC/SMODE is tied to VSS
.
PAF
Programmable
almost full
O
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when VCC/SMODE is tied to VCC
;
it is synchronized to WCLK when VCC/SMODE is tied to VSS
.
LD
Load
I
I
When LD is LOW, D017 (O017) are written (read) into (from) the program-
mable-flag-offset register.
FL/RT
First load/
retransmit
Dual-mode pin. Cascaded – The first device in the daisy chain will have FL tied to VSS
;
all other devices will have FL tied to VCC. In standard mode of width expansion, FL
is tied to VSS on all devices. Not Cascaded – Tied to VSS. Retransmit function is also
available in standalone mode by strobing RT.
WXI
RXI
Write expansion
input
I
I
Cascaded – Connected to WXO of previous device. Not cascaded – Tied to VSS
.
Read expansion
input
Cascaded – Connected to RXO of previous device. Not cascaded – Tied to VSS
.
Document Number: 001-45652 Rev. *B
Page 5 of 25
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