CY7C408A
CY7C409A
tion, which is signified by the OR signal being LOW at the
same time that the IR signal is HIGH. In this condition, the data
Architecture of the CY7C408A and CY7C409A
The CY7C408A and CY7C409A FIFOs consist of an array of
64 words of 8 or 9 bits each (which are implemented using a
dual-port RAM cell), a write pointer, a read pointer, and the
control logic necessary to generate the handshaking (SI/IR,
SO/OR) signals as well as the almost full/almost empty (AFE)
and half full (HF) flags. The handshaking signals operate in a
manner identical to those of the industry standard
CY7C401/402/403/404 FIFOs.
outputs (DO – DO ) will be LOW. The AFE flag will be HIGH
0
8
and the HF flag will be LOW.
Shifting Data Into the FIFO
The availability of an empty location is indicated by the HIGH
state of the input ready (IR) signal. When IR is HIGH a LOW
to HIGH transition on the shift in (SI) pin will clock the data on
the DI - DI inputs into the FIFO. Data propagates through the
0
8
device at the falling edge of SI.
Dual-Port RAM
The IR output will then go LOW, indicating that the data has
been sampled. The HIGH-to-LOW transition of the SI signal
initiates the LOW-to-HIGH transition of the IR signal if the FIFO
is not full. If the FIFO is full, IR will remain LOW.
The dual-port RAM architecture refers to the basic memory
cell used in the RAM. The cell itself enables the read and write
operations to be independent of each other, which is neces-
sary to achieve truly asynchronous operation of the inputs and
outputs. A second benefit is that the time required to increment
the read and write pointers is much less than the time that
would be required for data to propagate through the memory,
which it would have to do if the memory were implemented
using the conventional register array architecture.
Shifting Data Out of the FIFO
The availability of data at the outputs of the FIFO is indicated
by the HIGH state of the output ready (OR) signal. After the
FIFO is reset all data outputs (DO – DO ) will be in the LOW
0
8
state. As long as the FIFO remains empty, the OR signal will
be LOW and all SO pulses applied to it will be ignored. After
data is shifted into the FIFO, the OR signal will go HIGH. The
external control logic (designed by the user) should use the
HIGH state of the OR signal to generate a SO pulse. The data
outputs of the FIFO should be sampled with edge-sensitive
type D flip-flops (or equivalent), using the SO signal as the
clock input to the flip-flop.
Fall-Through and Bubble-Back
The time required for data to propagate from the input to the
output of an initially empty FIFO is defined as the fall-through
time.
The time required for an empty location to propagate from the
output to the input of an initially full FIFO is defined as the
bubble-back time.
AFE and HF Flags
The maximum rate at which data can be passed through the
FIFO (called the throughput) is limited by the fall-through time
when it is empty (or near empty) and by the bubble-back time
when it is full (or near full).
Two flags, almost full/almost empty (AFE) and half full (HF),
describe how many words are stored in the FIFO. AFE is HIGH
when there are 8 or fewer or 56 or more words stored in the
FIFO. Otherwise the AFE flag is LOW. HF is HIGH when there
are 32 or more words stored in the FIFO, otherwise the HF flag
is LOW. Flag transitions occur relative to the falling edges of
SI and SO (Figures 1 and 2).
The conventional definitions of fall-through and bubble-back
do not apply to the CY7C408A and CY7C409A FIFOs be-
cause the data is not physically propagated through the mem-
ory. The read and write pointers are incremented instead of
moving the data. However, the parameter is specified because
it does represent the worst-case propagation delay for the con-
trol signals. That is, the time required to increment the write
pointer and propagate a signal from the SI input to the OR
output of an empty FIFO or the time required to increment the
read pointer and propagate a signal from the SO input to the
IR output of a full FIFO.
Due to the asynchronous nature of the SI and SO signals, it is
possible to encounter specific timing relationships which may
cause short pulses on the AFE and HF flags. These pulses are
entirely due to the dynamic relationship of the SI and SO sig-
nals. The flags, however, will always settle to their correct state
after the appropriate delay (t
, t
, t
, or t
).
DHAFE DLAFE DHHF
DLHF
Therefore, use of level-sensitive rather than edge-sensitive
flag detection devices is recommended to avoid false flag en-
coding.
Resetting the FIFO
Upon power-up, the FIFO must be reset with a master reset
(MR) signal. This causes the device to enter the empty condi-
EMPTY
FULL
1
2
8
9
10
31
32
33
55
56
57
64
SHIFTIN
HF
C408A–17
AFE
Figure 1. Shifting Words In.
8
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