25A
CY7C225A
512 x 8 Registered PROM
• Direct replacement for bipolar PROMs
• Capable of withstanding greater than 2001V static
discharge
Features
• CMOS for optimum speed/power
• High speed
Functional Description
— 18 ns address set-up
The CY7C225A is a high-performance 512 word by 8 bit elec-
trically programmable read only memory packaged in a slim
300-mil plastic or hermetic DIP, 28-pin leadless chip carrier,
and 28-pin PLCC. The memory cells utilize proven EPROM
floating gate technology and byte-wide intelligent program-
ming algorithms.
— 12 ns clock to output
• Low power
— 495 mW (commercial)
— 660 mW (military)
• Synchronous and asynchronous output enables
• On-chip edge-triggered registers
• Buffered common PRESET and CLEAR inputs
• EPROM technology, 100% programmable
• Slim300-mil, 24-pinplasticor hermeticDIP, 28-pinLCC,
or 28-pin PLCC
• 5V ±10% VCC, commercial and military
• TTL-compatible I/O
The CY7C225A replaces bipolar devices and offers the advan-
tages of lower power, superior performance, and high pro-
gramming yield. The EPROM cell requires only 12.5V for the
supervoltage and low current requirements allow for gang pro-
gramming. The EPROM cells allow for each memory location
to be tested 100%, as each location is written into, erased, and
repeatedly exercised prior to encapsulation. Each PROM is
also tested for AC performance to guarantee that after custom-
er programming the product will meet AC specification limits.
Logic Block Diagram
Pin Configurations
DIP
Top View
O
O
7
A
0
1
24
A
V
CC
7
A
1
2
3
4
5
6
A
23
22
21
6
A
8
6
ROW
A
5
PS
PROGRAMMABLE
ARRAY
A
2
ADDRESS
MULTIPLEXER
A
4
E
O
O
5
A
3
A
20
19
3
CLR
8-BIT
EDGE-
TRIGGERED
REGISTER
E
S
A
2
A
4
4
A
1
7
18
17
16
CP
ADDRESS
DECODER
A
5
A
0
8
O
7
O
6
O
5
O
3
O
O
9
0
1
2
A
6
10
11
12
15
14
O
2
O
1
O
O
O
A
7
4
COLUMN
ADDRESS
GND
13
3
A
8
LCC/PLCC
Top View
O
0
S
R
CP
PS
CLR
CP
3
2 1 2827
4
26
25
E
CLR
A
4
5
6
7
8
9
A
24
23
22
21
20
19
3
E
S
A
2
CP
NC
O
A
1
E
S
A
0
NC
7
10
11
O
0
O
6
E
12 131415161718
Selection Guide
7C225A-18
7C225A-25
7C225A-30
7C225A-35
7C225A-40
Minimum Address Set-Up Time (ns)
Maximum Clock to Output (ns)
18
12
90
25
12
30
15
35
20
40
25
Maximum Operating
Current (mA)
Commercial
Military
90
90
90
120
120
120
120
Cypress Semiconductor Corporation
Document #: 38-04001 Rev. **
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
Revised March 4, 2002