Datasheet > 存储 > SRAM> CY7C1643KV18-400BZXC

CY7C1643KV18-400BZXC

更新时间： 2024-02-24 23:15:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
31页	861K
描述
144-Mbit QDRÂ® II SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)

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技术参数
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CY7C1643KV18-400BZXC 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	LBGA,	Reach Compliance Code：	compliant
ECCN代码：	3A991.B.2.A	HTS代码：	8542.32.00.41
风险等级：	1.96	其他特性：	PIPELINED ARCHITECTURE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e1
长度：	17 mm	内存密度：	150994944 bit
内存集成电路类型：	QDR SRAM	内存宽度：	18
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	8388608 words
字数代码：	8000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	8MX18	封装主体材料：	PLASTIC/EPOXY
封装代码：	LBGA	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	260	座面最大高度：	1.4 mm
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Silver/Copper (Sn/Ag/Cu)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	40	宽度：	15 mm
Base Number Matches：	1

CY7C1643KV18-400BZXC 数据手册

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CY7C1643KV18, CY7C1645KV18

144-Mbit QDR^®II+ SRAM Four-Word Burst

Architecture (2.0 Cycle Read Latency)

144-Mbit QDR^®II+ SRAM Four-Word Burst Architecture (2.0 Cycle Read Latency)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1 compatible test access port

Features

■ Separate independent read and write data ports

❐ Supports concurrent transactions

■ Phase locked loop (PLL) for accurate data placement

■ 450-MHz clock for high bandwidth

Configurations

■ Four-word burst for reducing address bus frequency

With Read Cycle Latency of 2.0 cycles:

CY7C1643KV18 – 8 M × 18

■ Double data rate (DDR) interfaces on both read and write ports

(data transferred at 900 MHz) at 450 MHz

CY7C1645KV18 – 4 M × 36

■ Available in 2.0-clock cycle latency

Functional Description

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

The CY7C1643KV18, and CY7C1645KV18 are 1.8-V

synchronous pipelined SRAMs, equipped with QDR II+

architecture. Similar to QDR II architecture, QDR II+ architecture

consists of two separate ports: the read port and the write port to

access the memory array. The read port has dedicated data

outputs to support read operations and the write port has

dedicated data inputs to support write operations. QDR II+

architecture has separate data inputs and data outputs to

completely eliminate the need to “turnaround” the data bus that

exists with common I/O devices. Each port is accessed through

a common address bus. Addresses for read and write addresses

are latched on alternate rising edges of the input (K) clock.

Accesses to the QDR II+ read and write ports are completely

independent of one another. To maximize data throughput, both

read and write ports are equipped with DDR interfaces. Each

address location is associated with four 18-bit words

(CY7C1643KV18), or 36-bit words (CY7C1645KV18) that burst

sequentially into or out of the device. Because data is transferred

into and out of the device on every rising edge of both input

clocks (K and K), memory bandwidth is maximized while

simplifying system design by eliminating bus “turnarounds”.

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

■ Data valid pin (QVLD) to indicate valid data on the output

■ Single multiplexed address input bus latches address inputs

for read and write ports

■ Separate port selects for depth expansion

■ Synchronous internally self-timed writes

■ Quad data rate (QDR^®) II+ operates with 2.0-cycle read latency

when DOFF is asserted high

■ Operates similar to QDR I device with one cycle read latency

when DOFF is asserted low

■ Available in × 18, and × 36 configurations

■ Full data coherency, providing most current data

[1]

■ Core V_DD= 1.8 V ± 0.1 V; I/O V_DDQ= 1.4 V to V_DD

❐ Supports both 1.5-V and 1.8-V I/O supply

Depth expansion is accomplished with port selects, which

enables each port to operate independently.

■ High-speed transceiver logic (HSTL) Inputs and variable drive

HSTL output buffers

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ Available in 165-ballfine pitch ball grid array (FBGA) package

(15 × 17 × 1.4 mm)

Selection Guide

Description

Maximum operating frequency

450 MHz

450

400 MHz Unit

400

860

MHz

Maximum operating current

× 18

× 36

940

1290

1170

Note

1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V

= 1.4 V to V

DDQ

Cypress Semiconductor Corporation

Document Number: 001-44059 Rev. *I

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised February 22, 2013

12 3 4 5 6 7...31

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与CY7C1643KV18-400BZXC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1643KV18-450BZC	CYPRESS	获取价格	144-Mbit QDRÂ® II SRAM Four-Word Burst Archit
CY7C1643KV18-450BZI	CYPRESS	获取价格	144-Mbit QDRÂ® II SRAM Four-Word Burst Archit
CY7C164-45DC	CYPRESS	获取价格	Standard SRAM, 16KX4, 45ns, CMOS, CDIP22, 0.300 INCH, CERDIP-22
CY7C164-45LC	CYPRESS	获取价格	Standard SRAM, 16KX4, 45ns, CMOS, CQCC22, CERAMIC, LCC-22
CY7C164-45LMB	CYPRESS	获取价格	Standard SRAM, 16KX4, 45ns, CMOS, CQCC22
CY7C164-45PC	CYPRESS	获取价格	Standard SRAM, 16KX4, 45ns, CMOS, PDIP22, 0.300 INCH, PLASTIC, DIP-22
CY7C164-45VC	CYPRESS	获取价格	Standard SRAM, 16KX4, 45ns, CMOS, PDSO24, PLASTIC, SOJ-24
CY7C164-45VCT	CYPRESS	获取价格	Standard SRAM, 16KX4, 45ns, CMOS, PDSO24, PLASTIC, SOJ-24
CY7C1645KV18	CYPRESS	获取价格	144-Mbit QDRÂ® II SRAM Four-Word Burst Archit
CY7C1645KV18-400BZXI	CYPRESS	获取价格	144-Mbit QDRÂ® II SRAM Four-Word Burst Archit

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