CY7C1648KV18
CY7C1650KV18
144-Mbit DDR II+ SRAM Two-Word Burst
Architecture (2.0 Cycle Read Latency)
144-Mbit DDR II+ SRAM Two-Word Burst Architecture (2.0 Cycle Read Latency)
■ Phase locked loop (PLL) for accurate data placement
Configurations
Features
■ 144-Mbit density (8 M × 18, 4 M × 36)
■ 450-MHz clock for high bandwidth
With Read Cycle Latency of 2.0 cycles:
■ Two-word burst for reducing address bus frequency
CY7C1648KV18 – 8 M × 18
CY7C1650KV18 – 4 M × 36
■ Double data rate (DDR) interfaces (data transferred at
900 MHz) at 450 MHz
Functional Description
■ Available in 2.0-clock cycle latency
The CY7C1648KV18, and CY7C1650KV18 are 1.8-V
synchronous pipelined SRAMs equipped with DDR II+
architecture. The DDR II+ consists of an SRAM core with
advanced synchronous peripheral circuitry. Addresses for read
and write are latched on alternate rising edges of the input (K)
clock. Write data is registered on the rising edges of both K and
K. Read data is driven on the rising edges of K and K. Each
address location is associated with two18-bit words
(CY7C1648KV18), or 36-bit words (CY7C1650KV18) that burst
sequentially into or out of the device.
■ Two input clocks (K and K) for precise DDR timing
❐ SRAM uses rising edges only
■ Echo clocks (CQ and CQ) simplify data capture in high-speed
systems
■ Data valid pin (QVLD) to indicate valid data on the output
■ Synchronous internally self-timed writes
■ DDR II+ operates with 2.0-cycle read latency when DOFF is
asserted high
Asynchronous inputs include an output impedance matching
input (ZQ). Synchronous data outputs (Q, sharing the same
physical pins as the data inputs D) are tightly matched to the two
output echo clocks CQ/CQ, eliminating the need for separately
capturing data from each individual DDR SRAM in the system
design.
■ Operates similar to DDR I device with one cycle read latency
when DOFF is asserted low
[1]
■ Core VDD = 1.8 V ± 0.1 V; I/O VDDQ = 1.4 V to VDD
❐ Supports both 1.5 V and 1.8 V I/O supply
All synchronous inputs pass through input registers controlled by
the K or K input clocks. All data outputs pass through output
registers controlled by the K or K input clocks. Writes are
conducted with on-chip synchronous self-timed write circuitry.
■ High-speed transceiver logic (HSTL) inputs and variable drive
HSTL output buffers
■ Available in 165-ball fine-pitch ball grid array (FBGA) package
(15 ×17 ×1.4 mm)
For a complete list of related documentation, click here.
■ Offered in both Pb-free and non Pb-free packages
■ JTAG 1149.1 compatible test access port
Selection Guide
Description
Maximum operating frequency
450 MHz
450
400 MHz Unit
400
730
900
MHz
mA
Maximum operating current
× 18 Not Offered
× 36
980
Note
1. The Cypress QDR II+ devices surpass the QDR consortium specification and can support V
= 1.4 V to V
.
DDQ
DD
Cypress Semiconductor Corporation
Document Number: 001-44061 Rev. *L
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised January 4, 2018