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CY7C1615KV18-333BZXC PDF预览

CY7C1615KV18-333BZXC

更新时间: 2024-01-15 21:44:34
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟静态存储器内存集成电路
页数 文件大小 规格书
32页 545K
描述
QDR SRAM, 4MX36, 0.45ns, CMOS, PBGA165, FBGA-165

CY7C1615KV18-333BZXC 技术参数

是否Rohs认证: 符合生命周期:Active
零件包装代码:BGA包装说明:LBGA, BGA165,11X15,40
针数:165Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
Factory Lead Time:1 week风险等级:2.3
最长访问时间:0.45 ns其他特性:PIPELINED ARCHITECTURE
最大时钟频率 (fCLK):333 MHzI/O 类型:SEPARATE
JESD-30 代码:R-PBGA-B165JESD-609代码:e1
长度:17 mm内存密度:150994944 bit
内存集成电路类型:QDR SRAM内存宽度:36
功能数量:1端子数量:165
字数:4194304 words字数代码:4000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:4MX36
输出特性:3-STATE封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装等效代码:BGA165,11X15,40
封装形状:RECTANGULAR封装形式:GRID ARRAY, LOW PROFILE
并行/串行:PARALLEL峰值回流温度(摄氏度):260
电源:1.5/1.8,1.8 V认证状态:Not Qualified
座面最大高度:1.4 mm最小待机电流:1.7 V
子类别:SRAMs最大供电电压 (Vsup):1.9 V
最小供电电压 (Vsup):1.7 V标称供电电压 (Vsup):1.8 V
表面贴装:YES技术:CMOS
温度等级:COMMERCIAL端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:40
宽度:15 mmBase Number Matches:1

CY7C1615KV18-333BZXC 数据手册

 浏览型号CY7C1615KV18-333BZXC的Datasheet PDF文件第1页浏览型号CY7C1615KV18-333BZXC的Datasheet PDF文件第2页浏览型号CY7C1615KV18-333BZXC的Datasheet PDF文件第4页浏览型号CY7C1615KV18-333BZXC的Datasheet PDF文件第5页浏览型号CY7C1615KV18-333BZXC的Datasheet PDF文件第6页浏览型号CY7C1615KV18-333BZXC的Datasheet PDF文件第7页 
CY7C1613KV18/CY7C1615KV18  
Contents  
Pin Configurations ...........................................................4  
Pin Definitions ..................................................................5  
Functional Overview ........................................................6  
Read Operations .........................................................6  
Write Operations .........................................................7  
Byte Write Operations .................................................7  
Single Clock Mode ......................................................7  
Concurrent Transactions .............................................7  
Depth Expansion .........................................................7  
Programmable Impedance ..........................................7  
Echo Clocks ................................................................7  
PLL ..............................................................................7  
Application Example ........................................................8  
Truth Table ........................................................................9  
Write Cycle Descriptions ...............................................10  
Write Cycle Descriptions ...............................................11  
IEEE 1149.1 Serial Boundary Scan (JTAG) ..................12  
Disabling the JTAG Feature ......................................12  
Test Access Port .......................................................12  
Performing a TAP Reset ...........................................12  
TAP Registers ...........................................................12  
TAP Instruction Set ...................................................12  
TAP Controller State Diagram .......................................14  
TAP Controller Block Diagram ......................................15  
TAP Electrical Characteristics ......................................15  
TAP AC Switching Characteristics ...............................16  
TAP Timing and Test Conditions ..................................17  
Identification Register Definitions ................................18  
Scan Register Sizes .......................................................18  
Instruction Codes ...........................................................18  
Boundary Scan Order ....................................................19  
Power Up Sequence in QDR II SRAM ...........................20  
Power Up Sequence .................................................20  
PLL Constraints .........................................................20  
Maximum Ratings ...........................................................21  
Operating Range .............................................................21  
Neutron Soft Error Immunity .........................................21  
Electrical Characteristics ...............................................21  
DC Electrical Characteristics .....................................21  
AC Electrical Characteristics .....................................23  
Capacitance ....................................................................23  
Thermal Resistance ........................................................23  
AC Test Loads and Waveforms .....................................23  
Switching Characteristics ..............................................24  
Switching Waveforms ....................................................26  
Ordering Information ......................................................27  
Ordering Code Definitions .........................................27  
Package Diagram ............................................................28  
Acronyms ........................................................................29  
Document Conventions .................................................29  
Units of Measure .......................................................29  
Document History Page .................................................30  
Sales, Solutions, and Legal Information ......................32  
Worldwide Sales and Design Support .......................32  
Products ....................................................................32  
PSoC® Solutions ......................................................32  
Cypress Developer Community .................................32  
Technical Support .....................................................32  
Document Number: 001-44273 Rev. *L  
Page 3 of 32  

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