CY7C1613KV18/CY7C1615KV18
Pin Definitions (continued)
Pin Name
I/O
Pin Description
DOFF
Input
PLL turn off Active low. Connecting this pin to ground turns off the PLL inside the device. The timings
in the PLL turned off operation differs from those listed in this datasheet. For normal operation, this pin
can be connected to a pull up through a 10 K or less pull-up resistor. The device behaves in QDR I
mode when the PLL is turned off. In this mode, the device can be operated at a frequency of up to
167 MHz with QDR I timing.
TDO
TCK
Output
Input
Input
Input
N/A
Test data-out (TDO) pin for JTAG.
Test clock (TCK) pin for JTAG.
TDI
Test data-in (TDI) pin for JTAG.
TMS
NC
Test mode select (TMS) pin for JTAG.
Not connected to the die. Can be tied to any voltage level.
Not connected to the die. Can be tied to any voltage level.
Reference voltage input. Static input used to set the reference level for HSTL inputs, outputs, and AC
NC/288M
VREF
N/A
Input-
Reference measurement points.
VDD
Power
Supply
Power supply inputs to the core of the device.
VSS
Ground
Ground for the device.
VDDQ
Power
Supply
Power supply inputs for the outputs of the device.
CY7C1613KV18 is described in the following sections. The
same basic descriptions apply to CY7C1615KV18.
Functional Overview
The CY7C1613KV18, CY7C1615KV18 are synchronous
pipelined burst SRAMs with a read port and a write port. The read
port is dedicated to read operations and the write port is
dedicated to write operations. Data flows into the SRAM through
the write port and flows out through the read port. These devices
multiplex the address inputs to minimize the number of address
pins required. By having separate read and write ports, the QDR
II completely eliminates the need to turn-around the data bus and
avoids any possible data contention, thereby simplifying system
design. Each access consists of four 18-bit data transfers in the
case of CY7C1613KV18, and four 36-bit data transfers in the
case of CY7C1615KV18 in two clock cycles.
Read Operations
The CY7C1613KV18 is organized internally as four arrays of
2 M × 18. Accesses are completed in a burst of four sequential
18-bit data words. Read operations are initiated by asserting
RPS active at the rising edge of the positive input clock (K). The
address presented to the address inputs is stored in the read
address register. Following the next
K clock rise, the
corresponding lowest order 18-bit word of data is driven onto the
Q[17:0] using C as the output timing reference. On the
subsequent rising edge of C, the next 18-bit data word is driven
onto the Q[17:0]. This process continues until all four 18-bit data
words have been driven out onto Q[17:0]. The requested data is
valid 0.45 ns from the rising edge of the output clock (C or C, or
K or K when in single clock mode). To maintain the internal logic,
each read access must be allowed to complete. Each read
access consists of four 18-bit data words and takes two clock
cycles to complete. Therefore, read accesses to the device can
not be initiated on two consecutive K clock rises. The internal
logic of the device ignores the second read request. Read
accesses can be initiated on every other K clock rise. Doing so
pipelines the data flow such that data is transferred out of the
device on every rising edge of the output clocks (C and C, or K
and K when in single clock mode).
This device operates with a read latency of one and half cycles
when DOFF pin is tied high. When DOFF pin is set low or
connected to VSS then device behaves in QDR I mode with a
read latency of one clock cycle.
Accesses for both ports are initiated on the positive input clock
(K). All synchronous input timing is referenced from the rising
edge of the input clocks (K and K) and all output timing is
referenced to the output clocks (C and C, or K and K when in
single clock mode).
All synchronous data inputs (D[x:0]) pass through input registers
controlled by the input clocks (K and K). All synchronous data
outputs (Q[x:0]) pass through output registers controlled by the
rising edge of the output clocks (C and C, or K and K when in
single clock mode).
When the read port is deselected, the CY7C1613KV18 first
completes the pending read transactions. Synchronous internal
circuitry automatically tristates the outputs following the next
rising edge of the positive output clock (C). This enables for a
seamless transition between devices without the insertion of wait
states in a depth expanded memory.
All synchronous control (RPS, WPS, BWS[x:0]) inputs pass
through input registers controlled by the rising edge of the input
clocks (K and K).
Document Number: 001-44273 Rev. *L
Page 6 of 32
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