CY7C1526V18-250BZC

更新时间： 2024-11-19 05:19:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器
页数	文件大小	规格书
23页	371K
描述
72-Mbit QDR⑩-II SRAM 4-Word Burst Architecture

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CY7C1526V18-250BZC 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	15 X 17 MM, 1.40 MM HEIGHT, MO-216, FBGA-165	针数：	165
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.92
最长访问时间：	0.45 ns	其他特性：	PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：	250 MHz	I/O 类型：	SEPARATE
JESD-30 代码：	R-PBGA-B165	JESD-609代码：	e0
长度：	17 mm	内存密度：	75497472 bit
内存集成电路类型：	QDR SRAM	内存宽度：	9
湿度敏感等级：	3	功能数量：	1
端子数量：	165	字数：	8388608 words
字数代码：	8000000	工作模式：	SYNCHRONOUS
最高工作温度：	70 °C	最低工作温度：
组织：	8MX9	输出特性：	3-STATE
封装主体材料：	PLASTIC/EPOXY	封装代码：	LBGA
封装等效代码：	BGA165,11X15,40	封装形状：	RECTANGULAR
封装形式：	GRID ARRAY, LOW PROFILE	并行/串行：	PARALLEL
峰值回流温度（摄氏度）：	220	电源：	1.5/1.8,1.8 V
认证状态：	Not Qualified	座面最大高度：	1.4 mm
最大待机电流：	0.38 A	最小待机电流：	1.7 V
子类别：	SRAMs	最大压摆率：	0.85 mA
最大供电电压 (Vsup)：	1.9 V	最小供电电压 (Vsup)：	1.7 V
标称供电电压 (Vsup)：	1.8 V	表面贴装：	YES
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	BALL
端子节距：	1 mm	端子位置：	BOTTOM
处于峰值回流温度下的最长时间：	NOT SPECIFIED	宽度：	15 mm
Base Number Matches：	1

CY7C1526V18-250BZC 数据手册

浏览型号CY7C1526V18-250BZC的Datasheet PDF文件第2页

浏览型号CY7C1526V18-250BZC的Datasheet PDF文件第3页

浏览型号CY7C1526V18-250BZC的Datasheet PDF文件第4页

浏览型号CY7C1526V18-250BZC的Datasheet PDF文件第5页

浏览型号CY7C1526V18-250BZC的Datasheet PDF文件第6页

浏览型号CY7C1526V18-250BZC的Datasheet PDF文件第7页

CY7C1511V18

CY7C1526V18

CY7C1513V18

CY7C1515V18

PRELIMINARY

72-Mbit QDR™-II SRAM 4-Word Burst

Architecture

Features

Functional Description

• Separate Independent Read and Write Data Ports

— Supports concurrent transactions

The CY7C1511V18, CY7C1526V18, CY7C1513V18, and

CY7C1515V18 are 1.8V Synchronous Pipelined SRAMs,

equipped with QDR-II architecture. QDR-II architecture

consists of two separate ports to access the memory array.

The Read port has dedicated Data Outputs to support Read

operations and the Write Port has dedicated Data Inputs to

support Write operations. QDR-II architecture has separate

data inputs and data outputs to completely eliminate the need

to “turn-around” the data bus required with common I/O

devices. Access to each port is accomplished through a

common address bus. Addresses for Read and Write

addresses are latched on alternate rising edges of the input

(K) clock. Accesses to the QDR-II Read and Write ports are

completely independent of one another. In order to maximize

data throughput, both Read and Write ports are equipped with

Double Data Rate (DDR) interfaces. Each address location is

associated with four 8-bit words (CY7C1511V18) or 9-bit

words (CY7C1526V18) or 18-bit words (CY7C1513V18) or

36-bit words (CY7C1515V18) that burst sequentially into or

out of the device. Since data can be transferred into and out

of the device on every rising edge of both input clocks (K and

K and C and C), memory bandwidth is maximized while simpli-

fying system design by eliminating bus “turn-arounds”.

• 250-MHz Clock for High Bandwidth

• 4-Word Burst for reducing address bus frequency

• Double Data Rate (DDR) interfaces on both Read and

Write Ports (data transferred at 500 MHz) at 250 MHz

• Two input clocks (K and K) for precise DDR timing

— SRAM uses rising edges only

• Two output clocks (C and C) accounts for clock skew

and flight time mismatching

• Echo clocks (CQ and CQ) simplify data capture in high

speed systems

• Single multiplexed address input bus latches address

inputs for both Read and Write ports

• Separate Port Selects for depth expansion

• Synchronous internally self-timed writes

• Available in ×8,x9, ×18, and ×36 configurations

• Full data coherency providing most current data

• Core Vdd=1.8(+/-0.1V);I/O Vddq=1.4V to Vdd)

• 15 × 17 x 1.4 mm 1.0-mm pitch FBGA package, 165-ball

Depth expansion is accomplished with Port Selects for each

(11 × 15 matrix)

port. Port selects allow each port to operate independently.

• Variable drive HSTL output buffers

• JTAG 1149.1 Compatible test access port

• Delay Lock Loop (DLL) for accurate data placement

Configurations

All synchronous inputs pass through input registers controlled

by the K or K input clocks. All data outputs pass through output

registers controlled by the C or C input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

CY7C1511V18–8M x 8

CY7C1526V18–8M x 9

CY7C1513V18–4M x 18

CY7C1515V18–2M x 36

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-05363 Rev. *A

Revised August 11, 2004

12 3 4 5 6 7...23

中文翻译

下载PDF

与CY7C1526V18-250BZC相关器件

型号	品牌	获取价格	描述	数据表
CY7C1526V18-250BZI	CYPRESS	获取价格	72-Mbit QDR⑩- II SRAM 4-Word Burst Architectu
CY7C1526V18-250BZXC	CYPRESS	获取价格	72-Mbit QDR⑩- II SRAM 4-Word Burst Architectu
CY7C1526V18-250BZXI	CYPRESS	获取价格	72-Mbit QDR⑩- II SRAM 4-Word Burst Architectu
CY7C1526V18-278BZC	CYPRESS	获取价格	72-Mbit QDR⑩- II SRAM 4-Word Burst Architectu
CY7C1526V18-278BZI	CYPRESS	获取价格	72-Mbit QDR⑩- II SRAM 4-Word Burst Architectu
CY7C1526V18-278BZXC	CYPRESS	获取价格	72-Mbit QDR⑩- II SRAM 4-Word Burst Architectu
CY7C1526V18-278BZXI	CYPRESS	获取价格	72-Mbit QDR⑩- II SRAM 4-Word Burst Architectu
CY7C1526V18-300BZC	CYPRESS	获取价格	72-Mbit QDR⑩- II SRAM 4-Word Burst Architectu
CY7C1526V18-300BZI	CYPRESS	获取价格	72-Mbit QDR⑩- II SRAM 4-Word Burst Architectu
CY7C1526V18-300BZXC	CYPRESS	获取价格	72-Mbit QDR⑩- II SRAM 4-Word Burst Architectu

与CY7C1526V18-250BZC相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

23
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

15
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

45
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

44

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1526V18-250BZC

CY7C1526V18-250BZC 技术参数

CY7C1526V18-250BZC 数据手册

与CY7C1526V18-250BZC相关器件

与CY7C1526V18-250BZC相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY7C1526V18-250BZC

CY7C1526V18-250BZC 技术参数

CY7C1526V18-250BZC 数据手册

与CY7C1526V18-250BZC相关器件

与CY7C1526V18-250BZC相关文章

您还可以找

您在本页遇到什么问题？