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CY7C1386DV25-250BZC PDF预览

CY7C1386DV25-250BZC

更新时间: 2024-01-29 16:59:50
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
30页 1165K
描述
18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM

CY7C1386DV25-250BZC 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:BGA
包装说明:LBGA,针数:165
Reach Compliance Code:compliantECCN代码:3A991.B.2.A
HTS代码:8542.32.00.41风险等级:5.84
最长访问时间:2.6 ns其他特性:PIPELINED ARCHITECTURE
JESD-30 代码:R-PBGA-B165JESD-609代码:e1
长度:15 mm内存密度:18874368 bit
内存集成电路类型:CACHE SRAM内存宽度:36
湿度敏感等级:3功能数量:1
端子数量:165字数:524288 words
字数代码:512000工作模式:SYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:512KX36封装主体材料:PLASTIC/EPOXY
封装代码:LBGA封装形状:RECTANGULAR
封装形式:GRID ARRAY, LOW PROFILE并行/串行:PARALLEL
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1.4 mm最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Silver/Copper (Sn/Ag/Cu)
端子形式:BALL端子节距:1 mm
端子位置:BOTTOM处于峰值回流温度下的最长时间:20
宽度:13 mmBase Number Matches:1

CY7C1386DV25-250BZC 数据手册

 浏览型号CY7C1386DV25-250BZC的Datasheet PDF文件第24页浏览型号CY7C1386DV25-250BZC的Datasheet PDF文件第25页浏览型号CY7C1386DV25-250BZC的Datasheet PDF文件第26页浏览型号CY7C1386DV25-250BZC的Datasheet PDF文件第27页浏览型号CY7C1386DV25-250BZC的Datasheet PDF文件第28页浏览型号CY7C1386DV25-250BZC的Datasheet PDF文件第29页 
CY7C1386DV25, CY7C1386FV25  
CY7C1387DV25, CY7C1387FV25  
Document History Page  
DocumentTitle:CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/CY7C1387FV2518-Mbit(512Kx36/1Mx18)Pipelined  
DCD Sync SRAM  
Document Number: 38-05548  
Orig. of  
Change  
REV.  
ECN NO. Issue Date  
Description of Change  
**  
254550  
288531  
See ECN  
See ECN  
RKF  
New data sheet  
*A  
SYT  
Edited description under “IEEE 1149.1 Serial Boundary Scan (JTAG)” for  
non-compliance with 1149.1  
Removed 225 Mhz Speed Bin  
Added Pb-free information for 100-Pin TQFP, 119 BGA and 165 FBGA  
Packages  
Added comment of ‘Pb-free BG packages availability’ below the Ordering  
Information  
*B  
326078  
See ECN  
PCI  
Address expansion pins/balls in the pinouts for all packages are modified as  
per JEDEC standard  
Added description on EXTEST Output Bus Tri-State  
Changed description on the Tap Instruction Set Overview and Extest  
Changed Device Width (23:18) for 119-BGA from 000110 to 101110  
Added separate row for 165 -FBGA Device Width (23:18)  
Changed ΘJA and ΘJC for TQFP Package from 31 and 6 °C/W to 28.66 and  
4.08 °C/W respectively  
Changed ΘJA and ΘJC for BGA Packagefrom 45 and 7 °C/W to 23.8 and 6.2  
°C/W respectively  
Changed ΘJA and ΘJC for FBGA Package from 46 and 3 °C/W to 20.7 and  
4.0 °C/W respectively  
Modified VOL, VOH test conditions  
Removed shading on DC Table for 200 MHz speed bin  
Removed comment of ‘Pb-free BG packages availability’ below the Ordering  
Information  
*C  
418125  
See ECN  
NXR  
Changed address of Cypress Semiconductor Corporation on Page# 1 from  
“3901 North First Street” to “198 Champion Court”  
Changed the description of IX from Input Load Current to Input Leakage  
Current on page# 18  
Changed the IX current values of MODE on page # 18 from –5 µA and 30 µA  
to –30 µA and 5 µA  
Changed the IX current values of ZZ on page # 18 from –30 µA and 5 µA  
to °5 µA and 30 µA  
Changed VIH < VDD to VIH < VDDon page # 18  
Updated Ordering Information Table  
*D  
*E  
475009  
793579  
See ECN  
See ECN  
VKN  
VKN  
Converted from Preliminary to Final.  
Added the Maximum Rating for Supply Voltage on VDDQ Relative to GND  
Changed tTH, tTL from 25 ns to 20 ns and tTDOV from 5 ns to 10 ns in TAP  
AC Switching Characteristics table.  
Updated the Ordering Information table.  
Added Part numbers CY7C1386FV25 and CY7C1387FV25  
Added footnote# 3 regarding Chip Enable  
Updated Ordering Information table  
Document Number: 38-05548 Rev. *E  
Page 30 of 30  

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