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CY7C1386DV25-167BZI PDF预览

CY7C1386DV25-167BZI

更新时间： 2024-01-28 18:39:34
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
30页 1165K
描述
18-Mbit (512K x 36/1M x 18) Pipelined DCD Sync SRAM

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中文翻译

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CY7C1386DV25-167BZI 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：BGA
包装说明：LBGA,针数：165
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.84
Is Samacsys：N最长访问时间：3.4 ns
其他特性：PIPELINED ARCHITECTUREJESD-30 代码：R-PBGA-B165
JESD-609代码：e1长度：15 mm
内存密度：18874368 bit内存集成电路类型：CACHE SRAM
内存宽度：36湿度敏感等级：3
功能数量：1端子数量：165
字数：524288 words字数代码：512000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：512KX36
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装形状：RECTANGULAR封装形式：GRID ARRAY, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
认证状态：Not Qualified座面最大高度：1.4 mm
最大供电电压 (Vsup)：2.625 V最小供电电压 (Vsup)：2.375 V
标称供电电压 (Vsup)：2.5 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Silver/Copper (Sn/Ag/Cu)端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：20宽度：13 mm
Base Number Matches：1

CY7C1386DV25-167BZI 数据手册

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CY7C1386DV25, CY7C1386FV25  
CY7C1387DV25, CY7C1387FV25  
Pin Definitions (continued)  
Name  
IO  
Description  
VSS  
Ground  
Ground for the core of the device.  
Ground for the IO circuitry.  
VSSQ  
VDDQ  
MODE  
IO Ground  
IO Power Supply Power supply for the IO circuitry.  
Input-  
Static  
Selects burst order. When tied to GND selects linear burst sequence. When tied  
to VDD or left floating selects interleaved burst sequence. This is a strap pin and  
must remain static during device operation. Mode pin has an internal pull up.  
TDO  
TDI  
JTAGserialoutput Serial data-out to the JTAG circuit. Delivers data on the negative edge of TCK.  
Synchronous  
If the JTAG feature is not used, this pin must be disconnected. This pin is not  
available on TQFP packages.  
JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG  
Synchronous  
feature is not used, this pin can be disconnected or connected to VDD. This pin is  
not available on TQFP packages.  
TMS  
JTAG serial input Serial data-in to the JTAG circuit. Sampled on the rising edge of TCK. If the JTAG  
Synchronous  
feature is not used, this pin can be disconnected or connected to VDD. This pin is  
not available on TQFP packages.  
TCK  
NC  
JTAG-  
Clock  
Clock input to the JTAG circuitry. If the JTAG feature is not used, this pin must  
be connected to VSS. This pin is not available on TQFP packages.  
–
–
No Connects. Not internally connected to the die  
NC/(36M, 72M, 144M,  
288M, 576M, 1G)  
These pins are not connected. They will be used for expansion to the 36M, 72M,  
144M, 288M, 576M, and 1G densities.  
Single Read Accesses  
Functional Overview  
This access is initiated when the following conditions are  
All synchronous inputs pass through input registers controlled  
by the rising edge of the clock. All data outputs pass through  
output registers controlled by the rising edge of the clock.  
satisfied at clock rise: (1) ADSP or ADSC is asserted LOW, (2)  
chip selects are all asserted active, and (3) the write signals  
(GW, BWE) are all deasserted HIGH. ADSP is ignored if CE1  
is HIGH. The address presented to the address inputs is  
stored into the address advancement logic and the address  
register while being presented to the memory core. The  
corresponding data is allowed to propagate to the input of the  
output registers. At the rising edge of the next clock the data  
is allowed to propagate through the output register and onto  
the data bus within tCO if OE is active LOW. The only exception  
occurs when the SRAM is emerging from a deselected state  
to a selected state, its outputs are always tri-stated during the  
first cycle of the access. After the first cycle of the access, the  
outputs are controlled by the OE signal. Consecutive single  
read cycles are supported.  
The  
CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/  
CY7C1387FV25 supports secondary cache in systems using  
either a linear or interleaved burst sequence. The interleaved  
burst order supports Pentium® and i486™ processors. The  
linear burst sequence is suited for processors that use a linear  
burst sequence. The burst order is user selectable, and is  
determined by sampling the MODE input. Accesses can  
initiated with either the processor address strobe (ADSP)  
be  
or  
the controller address strobe (ADSC). Address advancement  
through the burst sequence is controlled by the ADV input. A  
two-bit on-chip wraparound burst counter captures the first  
address in a burst sequence and automatically increments the  
address for the rest of the burst access.  
The  
CY7C1386DV25/CY7C1387DV25/CY7C1386FV25/  
Byte write operations are qualified with the byte write enable  
(BWE) and byte write select (BWX) inputs. A global write  
enable (GW) overrides all byte write inputs and writes data to  
all four bytes. All writes are simplified with on-chip  
synchronous self timed write circuitry.  
CY7C1387FV25 is a double-cycle deselect part. Once the  
SRAM is deselected at clock rise by the chip select and either  
ADSP or ADSC signals, its output will tri-state immediately  
after the next clock rise.  
Single Write Accesses Initiated by ADSP  
[2]  
Synchronous chip selects CE1, CE2, CE3  
and an  
This access is initiated when both of the following conditions  
are satisfied at clock rise: (1) ADSP is asserted LOW, and (2)  
chip select is asserted active. The address presented is  
loaded into the address register and the address  
advancement logic while being delivered to the memory core.  
asynchronous output enable (OE) provide for easy bank  
selection and output tri-state control. ADSP is ignored if CE1  
is HIGH.  
Document Number: 38-05548 Rev. *E  
Page 7 of 30  
1...45678910...30

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