CY7C1386D
CY7C1387D
PRELIMINARY
Pin Definitions
Name
I/O
Description
Address Inputs used to select one of the address locations. Sampled at the
A0, A1, A
Input-
[2]
Synchronous
rising edge of the CLK if ADSP or ADSC is active LOW, and CE1, CE2, and CE3
are sampled active. A1: A0 are fed to the two-bit counter.
.
BWA, BWB
BWC, BWD
Input-
Byte Write Select Inputs, active LOW. Qualified with BWE to conduct byte writes
Synchronous
to the SRAM. Sampled on the rising edge of CLK.
GW
Input-
Global Write Enable Input, active LOW. When asserted LOW on the rising edge
of CLK, a global write is conducted (ALL bytes are written, regardless of the values
on BWX and BWE).
Synchronous
BWE
CLK
CE1
Input-
Byte Write Enable Input, active LOW. Sampled on the rising edge of CLK. This
Synchronous
signal must be asserted LOW to conduct a byte write.
Input-
Clock
Clock Input. Used to capture all synchronous inputs to the device. Also used to
increment the burst counter when ADV is asserted LOW, during a burst operation.
Input-
Chip Enable 1 Input, active LOW. Sampled on the rising edge of CLK. Used in
conjunction with CE2 and CE3[2] to select/deselect the device. ADSP is ignored if
CE1 is HIGH. CE1 is sampled only when a new external address is loaded.
Synchronous
[2]
CE2
Input-
Chip Enable 2 Input, active HIGH. Sampled on the rising edge of CLK. Used in
conjunction with CE1 and CE3[2] to select/deselect the device. CE2 is sampled only
when a new external address is loaded.
Synchronous
[2]
CE3
Input-
Chip Enable 3 Input, active LOW. Sampled on the rising edge of CLK. Used in
Synchronous
conjunction with CE andCE to select/deselect the device.
Not connected for BGA.
1
Where referenced, CE3[2] is2assumed active throughout this document for BGA.
CE3 is sampled only when a new external address is loaded.
OE
Input-
Output Enable, asynchronous input, active LOW. Controls the direction of the
I/O pins. When LOW, the I/O pins behave as outputs. When deasserted HIGH, DQ
pins are tri-stated, and act as input data pins. OE is masked during the first clock of
a read cycle when emerging from a deselected state.
Asynchronous
ADV
Input-
Advance Input signal, sampled on the rising edge of CLK, active LOW. When
Synchronous
asserted, it automatically increments the address in a burst cycle.
ADSP
Input-
Address Strobe from Processor, sampled on the rising edge of CLK, active
LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized. ASDP is ignored when CE1 is
deasserted HIGH.
Synchronous
ADSC
Input-
Address Strobe from Controller, sampled on the rising edge of CLK, active
LOW. When asserted LOW, addresses presented to the device are captured in the
address registers. A1: A0 are also loaded into the burst counter. When ADSP and
ADSC are both asserted, only ADSP is recognized.
Synchronous
ZZ
Input-
ZZ “sleep” Input, active HIGH. When asserted HIGH places the device in a
non-time-critical “sleep” condition with data integrity preserved. For normal
operation, this pin has to be LOW or left floating. ZZ pin has an internal pull-down.
Asynchronous
I/O-
Bidirectional Data I/O lines. As inputs, they feed into an on-chip data register that
is triggered by the rising edge of CLK. As outputs, they deliver the data contained
in the memory location specified by the addresses presented during the previous
DQs, DQPX
Synchronous
cycle. The direction of the pins is controlled by OE. When OE
clock rise of the read
is asserted LOW, the pins behave as outputs. When HIGH, DQs and DQPX are
placed in a tri-state condition.
VDD
VSS
Power Supply
Ground
Power supply inputs to the core of the device.
Ground for the core of the device.
Ground for the I/O circuitry.
VSSQ
I/O Ground
Document #: 38-05545 Rev. **
Page 6 of 30
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