1CY7C1380BV25
CY7C1380BV25
CY7C1382BV25
PRELIMINARY
512K x 36 / 1 Mb x 18 Pipelined SRAM
(CLK). The synchronous inputs include all addresses, all data
inputs, address-pipelining Chip Enable (CE), burst control in-
puts (ADSC, ADSP, and ADV), Write Enables (BWa, BWb,
Features
• Fast clock speed: 200,166, 150, 133 MHz
• Provide high-performance 3-1-1-1 access rate
• Fast OE access times: 3.0,3.2, 3.4, 3.8, 4.2 ns
• Optimal for depth expansion
BWc, BWd and BWE), and global write (GW).
Asynchronous inputs include the output enable (OE) and Burst
Mode Control (MODE). The data (DQa,b,c,d) and the data par-
ity (DQPa,b,c,d) outputs, enabled by OE, are also asynchro-
nous.
• 2.5V (±5%) Operation
• Common data inputs and data outputs
• Byte Write Enable and Global Write control
• Chip enable for address pipeline
DQa,b,c,d and DQPa,b,c,d apply to CY7C1380BV25 and DQa,b
and DQPa,b apply to CY7C1382BV25. a, b, c, d each are of 8
bits wide in the case of DQ and 1 bit wide in the case of DP.
• Address, data, and control registers
• Internally self-timed WRITE CYCLE
Addresses and chip enables are registered with either Ad-
dress Status Processor (ADSP) or Address Status Controller
(ADSC) input pins. Subsequent burst addresses can be inter-
nally generated as controlled by the Burst Advance Pin (ADV).
• Burst control pins (interleaved or linear burst se-
quence)
• Automatic power-down for portable applications
• High-density, high-speed packages
• JTAG boundary scan for BGA packaging version
Address, data inputs, and write controls are registered on-chip
to initiate self-timed WRITE cycle. WRITE cycles can be one
to four bytes wide as controlled by the write control inputs.
Individual byte write allows individual byte to be written. BWa
controls DQa and DQPa. BWb controls DQb and DQPb. BWc
controls DQc and DQPd. BWd controls DQd-DQd and DQPd.
BWa, BWb BWc, and BWd can be active only with BWE being
LOW. GW being LOW causes all bytes to be written. WRITE
pass-through capability allows written data available at the out-
put for the immediately next READ cycle. This device also in-
corporates pipelined enable circuit for easy depth expansion
without penalizing system performance.
Functional Description
The Cypress Synchronous Burst SRAM family employs
high-speed, low-power CMOS designs using advanced sin-
gle-layer polysilicon, triple-layer metal technology. Each mem-
ory cell consists of six transistors.
The CY7C1382BV25 and CY7C1380BV25 SRAMs integrate
1,048,576x18 and 524,288x36 SRAM cells with advanced
synchronous peripheral circuitry and a 2-bit counter for inter-
nal burst operation. All synchronous inputs are gated by reg-
isters controlled by a positive-edge-triggered clock input
All inputs and outputs of the CY7C1380BV25 and the
CY7C1382BV25 are JEDEC standard JESD8-5 compatible.
Selection Guide
200 MHz
3.0
166 MHz
3.4
150 MHz
3.8
133 MHz
4.2
Maximum Access Time (ns)
Maximum Operating Current (mA)
Commercial
280
230
190
160
Maximum CMOS Standby Current (mA)
30
30
30
30
Shaded areas contain advance information.
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
July 5, 2001
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