CY7C1031
CY7C1032
64K x 18 Synchronous Cache RAM
Features
Functional Description
• Supports 66-MHz Pentium® microprocessor cache
The CY7C1031 and CY7C1032 are 64K by 18 synchronous
cache RAMs designed to interface with high-speed micropro-
cessors with minimum glue logic. Maximum access delay from
clock rise is 8.5 ns. A 2-bit on-chip counter captures the first
address in a burst and increments the address automatically
for the rest of the burst access.
systems with zero wait states
• 64K by 18 common I/O
• Fast clock-to-output times
— 8.5 ns
The CY7C1031 is designed for Intel® Pentium and i486
• Two-bit wraparound counter supporting Pentium
CPU-based systems; its counter follows the burst sequence of
microprocessor and 486 burst sequence (CY7C1031)
the Pentium and the i486 processors. The CY7C1032 is archi-
tected for processors with linear burst sequences. Burst
accesses can be initiated with the processor address strobe
(ADSP) or the cache controller address strobe (ADSC) inputs.
Address advancement is controlled by the address
advancement (ADV) input.
• Two-bit wraparound counter supporting linear burst
sequence (CY7C1032)
• Separate processor and controller address strobes
• Synchronous self-timed write
• Direct interface with the processor and external cache
A synchronous self-timed write mechanism is provided to
simplify the write interface. A synchronous chip select input
and an asynchronous output enable input provide easy control
for bank selection and output three-state control.
controller
• Asynchronous output enable
• I/Os capable of 3.3V operation
• JEDEC-standard pinout
• 52-pin PLCC packaging
Logic Block Diagram
Pin Configuration
PLCC
18
Top View
DATA
IN
REGISTER
16
14
A
15
–A
0
7
6
5
4
3
2
1
52 51 50 49 48 47
46
9
9
ADDR
REG
[1]
DQ
DQ
DP
DQ
DQ
V
V
8
9
8
9
0
14
2
45
44
43
42
41
40
39
38
37
36
35
34
7
6
16
V
CCQ
10
11
12
13
14
15
16
17
18
19
20
2
V
SSQ
CCQ
SSQ
ADV
DQ
ADV
LOGIC
10
11
12
13
64K X 9
64K X 9
RAM ARRAY RAM ARRAY
DQ
DQ
DQ
V
DQ
7C1031
7C1032
5
4
3
2
DQ
DQ
DQ
V
V
DQ
DQ
SSQ
WH
WL
CLK
V
CCQ
SSQ
CCQ
ADSP
ADSC
CS
WH
WL
DQ
14
15
TIMING
CONTROL
DQ
1
0
[1]
9
9
DP
1
2122 23 24 25 26 27 28 29 30 31 32 33
18
DQ – DQ
15
0
DP – DP
1
0
OE
Selection Guide
7C1031-8
7C1032-8
7C1031-10
7C1032-10
7C1031-12
Unit
ns
Maximum Access Time
8.5
10
12
Maximum Operating Current
Commercial
280
280
230
mA
Note:
1. DP and DP are functionally equivalent to DQ .
0
1
x
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose, CA 95134
•
408-943-2600
Document #: 38-05278 Rev. *A
Revised April 1, 2004