Datasheet > CY7C09169AV

CY7C09169AV

更新时间： 2022-04-23 23:00:11

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
17页	320K
描述
3.3V 8K/16K x 9 Synchronous Dual Port Static RAM

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中文翻译

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数据手册

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CY7C09169AV 数据手册

CY7C09159AV

CY7C09169AV

Switching Waveforms (continued)

Counter Reset (Pipelined Outputs)^{[9, 16, 22, 23]}

CYC2

CH2

CL2

CLK

ADDRESS

n+1

INTERNAL

ADDRESS

n+1

R/W

ADS

SAD

HAD

SCN

HCN

CNTEN

HRST

SRST

CNTRST

DATA

OUT

COUNTER

RESET

WRITE

ADDRESS 0

READ

ADDRESS 0

READ

ADDRESS 1

READ

ADDRESS n

Notes:

22. CE₀= V_IL; CE₁= V_IH

23. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset.

Document #: 38-06053 Rev. **

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