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CY7C006-35JC PDF预览

CY7C006-35JC

更新时间： 2024-09-30 03:08:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
16页 322K
描述
16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy

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CY7C006-35JC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：LCC包装说明：PLASTIC, LCC-68
针数：68Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.41
风险等级：5.75最长访问时间：35 ns
其他特性：INTERRUPT FLAGI/O 类型：COMMON
JESD-30 代码：S-PQCC-J68JESD-609代码：e0
长度：24.2316 mm内存密度：131072 bit
内存集成电路类型：DUAL-PORT SRAM内存宽度：8
功能数量：1端口数量：2
端子数量：68字数：16384 words
字数代码：16000工作模式：ASYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：16KX8输出特性：3-STATE
可输出：YES封装主体材料：PLASTIC/EPOXY
封装代码：QCCJ封装等效代码：LDCC68,1.0SQ
封装形状：SQUARE封装形式：CHIP CARRIER
并行/串行：PARALLEL峰值回流温度（摄氏度）：225
电源：5 V认证状态：Not Qualified
座面最大高度：5.08 mm最大待机电流：0.000015 A
最小待机电流：4.5 V子类别：SRAMs
最大压摆率：0.21 mA最大供电电压 (Vsup)：5.5 V
最小供电电压 (Vsup)：4.5 V标称供电电压 (Vsup)：5 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：J BEND端子节距：1.27 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：24.2316 mmBase Number Matches：1

CY7C006-35JC 数据手册

 浏览型号CY7C006-35JC的Datasheet PDF文件第2页浏览型号CY7C006-35JC的Datasheet PDF文件第3页浏览型号CY7C006-35JC的Datasheet PDF文件第4页浏览型号CY7C006-35JC的Datasheet PDF文件第5页浏览型号CY7C006-35JC的Datasheet PDF文件第6页浏览型号CY7C006-35JC的Datasheet PDF文件第7页 
with Sem, In t, Busy  
CY7C006  
CY7C016  
16K x 8/9 Dual-Port Static RAM  
with Sem, Int, Busy  
schemes are included on the CY7C006/016 to handle situa-  
tions when multiple processors access the same piece of data.  
Two ports are provided, permitting independent, asynchro-  
nous access for reads and writes to any location in memory.  
Features  
• True dual-ported memory cells which allow  
simultaneous reads of the same memory location  
The CY7C006/016 can be utilized as  
a standalone  
• 16K x 8 organization (CY7C006)  
• 16K x 9 organization (CY7C016)  
• 0.65-micron CMOS for optimum speed/power  
• High-speed access: 15 ns  
128-/144-Kbit dual-port static RAM or multiple devices can be  
combined in order to function as a 16-/18-bit or wider mas-  
ter/slave dual-port static RAM. An M/S pin is provided for im-  
plementing 16-/18-bit or wider memory applications without  
the need for separate master and slave devices or additional  
discrete logic. Application areas include interprocessor/multi-  
processor designs, communications status buffering, and du-  
al-port video/graphics memory.  
• Low operating power: I = 140 mA (typ.)  
CC  
• Fully asynchronous operation  
• Automatic power-down  
• TTL compatible  
Each port has independent control pins: Chip Enable (CE),  
Read or Write Enable (R/W), and Output Enable (OE). Two  
flags, BUSY and INT, are provided on each port. BUSY signals  
that the port is trying to access the same location currently  
being accessed by the other port. The Interrupt flag (INT) per-  
mits communication between ports or systems by means of a  
mail box. The semaphores are used to pass a flag, or token,  
from one port to the other to indicate that a shared resource is  
in use. The semaphore logic is comprised of eight shared  
latches. Only one side can control the latch (semaphore) at  
any time. Control of a semaphore indicates that a shared re-  
source is in use. An automatic power-down feature is con-  
trolled independently on each port by a Chip Enable (CE) pin  
or SEM pin.  
• Expandable data bus to 16/18 bits or more using  
Master/Slave chip select when using more than one  
device  
• Busy arbitration scheme provided  
• Semaphores included to permit software handshaking  
between ports  
• INT flag for port-to-port communication  
• Available in 68-pin PLCC (7C006), 64-pin (7C006) and  
80-pin (7C016) TQFP  
• Pin compatible and functional equivalent to  
IDT7006/IDT7016  
Functional Description  
The CY7C006 and CY7C016 are available in 68-pin PLCC  
(CY7C006), 64-pin (CY7C006) TQFP, and 80-pin (CY7C016) TQFP.  
The CY7C006 and CY7C016 are high-speed CMOS 16K x 8  
and 16K x 9 dual-port static RAMs. Various arbitration  
R/W  
L
R/W  
R
Logic Block Diagram  
CE  
OE  
CE  
OE  
L
R
R
L
(7C016)I/O  
I/O  
I/O (7C016)  
8R  
8L  
7L  
I/O  
7R  
I/O  
CONTROL  
I/O  
CONTROL  
I/O  
0L  
I/O  
0R  
[1,2]  
BUSY  
R
[1,2]  
L
BUSY  
A
13L  
A
A
13R  
0R  
ADDRESS  
DECODER  
ADDRESS  
DECODER  
MEMORY  
ARRAY  
A
0L  
INTERRUPT  
SEMAPHORE  
ARBITRATION  
CE  
OE  
L
L
L
CE  
R
OE  
R
R/W  
R/W  
R
SEM  
SEM  
R
L
[2]  
C006-1  
[2]  
INT  
R
INT  
L
M/S  
Notes:  
1. BUSY is an output in master mode and an input in slave mode.  
2. Interrupt: push-pull output and requires no pull-up resistor.  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose  
•
CA 95134  
•
408-943-2600  
December 22, 1999  
1234567...16

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 		16K x 8/9 Dual-Port Static RAM with Sem, Int, Busy
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