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CY7C006A-15JI PDF预览

CY7C006A-15JI

更新时间: 2024-09-30 19:43:07
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器内存集成电路
页数 文件大小 规格书
20页 335K
描述
Dual-Port SRAM, 16KX8, 15ns, CMOS, PQCC68, PLASTIC, LCC-68

CY7C006A-15JI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:LCC包装说明:PLASTIC, LCC-68
针数:68Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.82最长访问时间:15 ns
I/O 类型:COMMONJESD-30 代码:S-PQCC-J68
JESD-609代码:e0长度:24.2316 mm
内存密度:131072 bit内存集成电路类型:DUAL-PORT SRAM
内存宽度:8湿度敏感等级:1
功能数量:1端口数量:2
端子数量:68字数:16384 words
字数代码:16000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:16KX8输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:QCCJ
封装等效代码:LDCC68,1.0SQ封装形状:SQUARE
封装形式:CHIP CARRIER并行/串行:PARALLEL
峰值回流温度(摄氏度):235电源:5 V
认证状态:Not Qualified座面最大高度:5.08 mm
最大待机电流:0.0005 A最小待机电流:4.5 V
子类别:SRAMs最大压摆率:0.305 mA
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:TIN LEAD端子形式:J BEND
端子节距:1.27 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:24.2316 mm
Base Number Matches:1

CY7C006A-15JI 数据手册

 浏览型号CY7C006A-15JI的Datasheet PDF文件第2页浏览型号CY7C006A-15JI的Datasheet PDF文件第3页浏览型号CY7C006A-15JI的Datasheet PDF文件第4页浏览型号CY7C006A-15JI的Datasheet PDF文件第5页浏览型号CY7C006A-15JI的Datasheet PDF文件第6页浏览型号CY7C006A-15JI的Datasheet PDF文件第7页 
CY7C006A  
CY7C007A  
CY7C017A32K/16K  
x 8, 32K x 9  
Dual-Port Static RAM  
CY7C006A/CY7C007A  
CY7C016A/CY7C017A  
32K/16K x 8, 32K x 9  
Dual-Port Static RAM  
Features  
• True dual-ported memory cells which allow  
• Automatic power-down  
simultaneous access of the same memory location  
• Expandable data bus to 16/18 bits or more using  
Master/Slave chip select when using more than one  
device  
• 16K x 8 organization (CY7C006A)  
• 32K x 8 organization (CY7C007A)  
• 16K x 9 organization (CY7C016A)  
• 32K x 9 organization (CY7C017A)  
• 0.35-micron CMOS for optimum speed/power  
• High-speed access: 12[1]/15/20 ns  
• Low operating power  
• On-chip arbitration logic  
• Semaphores included to permit software handshaking  
between ports  
• INT flags for port-to-port communication  
• Pin select for Master or Slave  
• Commercial temperature range  
— Active: ICC = 180 mA (typical)  
— Standby: ISB3 = 0.05 mA (typical)  
• Fully asynchronous operation  
• Available in 68-pin PLCC (CY7C006A, CY7C007A and  
CY7C017A), 64-pin TQFP (CY7C006A), and in 80-pin  
TQFP (CY7C007A and CY7C016A)  
• Pb-Free packages available  
Logic Block Diagram  
R/WL  
CEL  
R/WR  
CER  
OEL  
OER  
8/9  
[2]  
8/9  
[2]  
I/O0L–I/O7/8L  
I/O0R–I/O7/8R  
I/O  
Control  
I/O  
Control  
14/15  
14/15  
Address  
Decode  
Address  
Decode  
True Dual-Ported  
[4]  
[4]  
A0L–A13/14L  
A0R–A13/14R  
RAM Array  
14/15  
14/15  
[4]  
[4]  
A
0L–A13/14L  
A0R–A13/14R  
CER  
CEL  
Interrupt  
Semaphore  
Arbitration  
OEL  
OER  
R/WL  
SEML  
R/WR  
SEMR  
[3] BUSYR  
INTR  
[3]  
BUSYL  
INTL  
M/S  
Notes:  
1. See page 7 for Load Conditions.  
2. I/O –I/O for x8 devices; I/O –I/O for x9 devices.  
0
7
0
8
3. BUSY is an output in master mode and an input in slave mode.  
4. A –A for 16K; A –A for 32K devices.  
0
13  
0
14  
Cypress Semiconductor Corporation  
Document #: 38-06045 Rev. *D  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 11, 2005  

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