Datasheet > CY7B991.5JXCT

CY7B991.5JXCT

更新时间： 2022-12-28 02:41:09

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
19页	514K
描述
Programmable Skew Clock Buffer

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数据手册

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CY7B991.5JXCT 数据手册

CY7B991

CY7B992

Pin Configuration

PLCC/LCC

32 31 30

2F0

GND

1F1

1F0

3F1

4F0

4F1

CCQ

CY7B991

CY7B992

CCN

4Q1

1Q0

1Q1

GND

4Q0

GND

14 15 16 17 18 19 20

Pin Definitions

Signal Name

Description

REF

Reference frequency input. This input supplies the frequency and timing against which all functional

variations are measured.

PLL feedback input (typically connected to one of the eight outputs).

Three level frequency range select. See Table 1.

Three level function select inputs for output pair 1 (1Q0, 1Q1). See Table 2.

Three level function select inputs for output pair 2 (2Q0, 2Q1). See Table 2.

Three level function select inputs for output pair 3 (3Q0, 3Q1). See Table 2.

Three level function select inputs for output pair 4 (4Q0, 4Q1). See Table 2.

Three level select. See “Test Mode” on page 4 under the “Block Diagram Description” on page 3.

Output pair 1. See Table 2.

1F0, 1F1

2F0, 2F1

3F0, 3F1

4F0, 4F1

TEST

1Q0, 1Q1

2Q0, 2Q1

3Q0, 3Q1

4Q0, 4Q1

V_CCN

Output pair 2. See Table 2.

Output pair 3. See Table 2.

Output pair 4. See Table 2.

PWR

Power supply for output drivers.

V_CCQ

Power supply for internal circuitry.

GND

Ground.

Document Number: 38-07138 Rev. *B

Page 2 of 19

123 4 5 6 7...19

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