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CY7B991.5JXCT PDF预览

CY7B991.5JXCT

更新时间: 2022-12-28 02:41:09
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赛普拉斯 - CYPRESS 时钟
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19页 514K
描述
Programmable Skew Clock Buffer

CY7B991.5JXCT 数据手册

 浏览型号CY7B991.5JXCT的Datasheet PDF文件第3页浏览型号CY7B991.5JXCT的Datasheet PDF文件第4页浏览型号CY7B991.5JXCT的Datasheet PDF文件第5页浏览型号CY7B991.5JXCT的Datasheet PDF文件第7页浏览型号CY7B991.5JXCT的Datasheet PDF文件第8页浏览型号CY7B991.5JXCT的Datasheet PDF文件第9页 
CY7B991  
CY7B992  
Electrical Characteristics  
Over the Operating Range[6]  
CY7B991  
CY7B992  
Min Max  
Parameter  
Description  
Test Conditions  
VCC = Min IOH = –16 mA  
VCC = Min, IOH =–40 mA  
VCC = Min, IOL = 46 mA  
VCC = Min, IOL = 46 mA  
Min  
Max  
Unit  
VOH  
Output HIGH Voltage  
2.4  
V
VCC–0.75  
VOL  
Output LOW Voltage  
0.45  
V
0.45  
VCC  
VIH  
VIL  
Input HIGH Voltage  
(REF and FB inputs only)  
2.0  
–0.5  
VCC  
0.8  
VCC  
V
V
1.35  
Input LOW Voltage  
(REF and FB inputs only)  
–0.5  
1.35  
VCC  
VIHH  
VIMM  
VILL  
IIH  
Three Level Input HIGH  
Voltage (Test, FS, xFn)[10]  
Min VCC Max  
Min VCC Max  
VCC – 0.85  
VCC  
VCC – 0.85  
V
Three Level Input MID  
VCC/2 –  
500 mV  
VCC/2 +  
500 mV  
VCC/2 –  
500 mV  
VCC/2 +  
500 mV  
V
Voltage (Test, FS, xFn)[10]  
Three Level Input LOW  
Min VCC  
Maximum  
0.0  
–500  
–50  
0.85  
0.0  
–500  
–50  
0.85  
V
Voltage (Test, FS, xFn)[10]  
InputHIGHLeakageCurrent VCC = Max, VIN = Max.  
(REF and FB inputs only)  
10  
10  
μA  
μA  
μA  
μA  
μA  
mA  
mA  
IIL  
Input LOW Leakage Current VCC = Max, VIN = 0.4V  
(REF and FB inputs only)  
IIHH  
IIMM  
IILL  
Input HIGH Current  
(Test, FS, xFn)  
VIN = VCC  
VIN = VCC/2  
VIN = GND  
200  
50  
200  
50  
Input MID Current  
(Test, FS, xFn)  
Input LOW Current  
(Test, FS, xFn)  
–200  
–250  
–200  
N/A  
IOS  
Output Short Circuit  
Current[8]  
VCC = Max, VOUT  
= GND (25°C only)  
ICCQ  
Operating Current Used by VCCN =VCCQ =Max, Com’l  
Internal Circuitry  
85  
90  
85  
90  
All Input  
Selects Open  
Mil/Ind  
ICCN  
Output Buffer Current per  
Output Pair[9]  
VCCN = VCCQ = Max,  
14  
19  
mA  
IOUT = 0 mA  
Input Selects Open, fMAX  
PD  
Power Dissipation per  
Output Pair[10]  
VCCN = VCCQ = Max,  
78  
104[11]  
mW  
IOUT = 0 mA  
Input Selects Open, fMAX  
Notes  
6. For more information see “Group A Subgroup Testing” on page 17.  
7. These inputs are normally wired to V , GND, or left unconnected (actual threshold voltages vary as a percentage of V ). Internal termination resistors hold  
CC  
CC  
unconnected inputs at V /2. If these inputs are switched, the function and timing of the outputs may glitch and the PLL may require an additional t  
CC  
time before  
LOCK  
all datasheet limits are achieved.  
8. CY7B991 must be tested one output at a time, output shorted for less than one second, less than 10% duty cycle. Room temperature only. CY7B992 outputs must  
not be shorted to GND. Doing so may cause permanent damage.  
9. Total output current per output pairis approximated by the following expression that includes device current plus load current:  
CY7B991:  
CY7B992:  
Where  
I
I
= [(4 + 0.11F) + [((835 – 3F)/Z) + (.0022FC)]N] x 1.1  
= [(3.5+ 0.17F) + [((1160 – 2.8F)/Z) + (.0025FC)]N] x 1.1  
CCN  
CCN  
F = frequency in MHz; C = capacitive load in pF; Z = line impedance in ohms; N = number of loaded outputs; 0, 1, or 2; FC = F < C.  
10. Total power dissipation per output pair can be approximated by the following expression that includes device power dissipation plus power dissipation due to the load  
circuit:  
CY7B991:PD = [(22 + 0.61F) + [((1550 – 2.7F)/Z) + (.0125FC)]N] x 1.1  
CY7B992:PD = [(19.25+ 0.94F) + [((700 + 6F)/Z) + (.017FC)]N] x 1.1  
See note 9 for variable definition.  
11. Applies to REF and FB inputs only. Tested initially and after any design or process changes that may affect these parameters.  
Document Number: 38-07138 Rev. *B  
Page 6 of 19  

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