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CY62126BVLL-70BAI PDF预览

CY62126BVLL-70BAI

更新时间: 2024-02-04 22:19:52
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
9页 191K
描述
64K x 16 Static RAM

CY62126BVLL-70BAI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:BGA包装说明:7 X 7 MM, FBGA-48
针数:48Reach Compliance Code:not_compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.76最长访问时间:70 ns
I/O 类型:COMMONJESD-30 代码:S-PBGA-B48
JESD-609代码:e0长度:7 mm
内存密度:1048576 bit内存集成电路类型:STANDARD SRAM
内存宽度:16功能数量:1
端子数量:48字数:65536 words
字数代码:64000工作模式:ASYNCHRONOUS
最高工作温度:85 °C最低工作温度:-40 °C
组织:64KX16输出特性:3-STATE
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA48,6X8,30封装形状:SQUARE
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):NOT SPECIFIED电源:3/3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.000015 A最小待机电流:2 V
子类别:SRAMs最大压摆率:0.015 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:BALL
端子节距:0.75 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
Base Number Matches:1

CY62126BVLL-70BAI 数据手册

 浏览型号CY62126BVLL-70BAI的Datasheet PDF文件第2页浏览型号CY62126BVLL-70BAI的Datasheet PDF文件第3页浏览型号CY62126BVLL-70BAI的Datasheet PDF文件第4页浏览型号CY62126BVLL-70BAI的Datasheet PDF文件第5页浏览型号CY62126BVLL-70BAI的Datasheet PDF文件第6页浏览型号CY62126BVLL-70BAI的Datasheet PDF文件第7页 
CY62126BV  
64K x 16 Static RAM  
(BLE) is LOW, then data from I/O pins (I/O through I/O ), is  
Features  
1
8
written into the location specified on the address pins (A  
0
• 2.7V–3.6V operation  
through A ). If Byte High Enable (BHE) is LOW, then data  
15  
from I/O pins (I/O through I/O ) is written into the location  
• CMOS for optimum speed/power  
• Low active power (70 ns, LL version)  
— 54 mW (max.) (15 mA)  
9
16  
specified on the address pins (A through A ).  
0
15  
Reading from the device is accomplished by taking Chip En-  
able (CE) and Output Enable (OE) LOW while forcing the write  
enable (WE) HIGH. If Byte Low Enable (BLE) is LOW, then  
data from the memory location specified by the address pins  
will appear on I/O to I/O . If Byte High Enable (BHE) is LOW,  
• Low standby power (70 ns, LL version)  
— 54 W (max.) (15 A)  
µ
µ
• Automatic power-down when deselected  
• Independent control of Upper and Lower Bytes  
• Available in 44-pin TSOP II (forward) and fBGA  
1
8
then data from memory will appear on I/O to I/O . See the  
9
16  
truth table at the back of this data sheet for a complete descrip-  
tion of read and write modes.  
Functional Description  
The input/output pins (I/O through I/O ) are placed in a  
1
16  
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), the BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
The CY62126BV is a high-performance CMOS static RAM or-  
ganized as 65,536 words by 16 bits. This device has an auto-  
matic power-down feature that significantly reduces power  
consumption by 99% when deselected. The device enters  
power-down mode when CE is HIGH.  
The CY62126BV is available in standard 44-pin TSOP Type II  
(forward pinout) and fBGA packages.  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
Logic Block Diagram  
Pin  
Configurations  
TSOP II (Forward)  
Top View  
DATA IN DRIVERS  
44  
1
A
4
A
5
A12  
A11  
A10  
A9  
A7  
A6  
43  
42  
41  
40  
39  
38  
A
A
2
3
4
5
6
3
6
A
A
2
7
OE  
A
1
BHE  
BLE  
I/O  
I/O  
15  
I/O  
A
0
CE  
64K x 16  
I/O  
7
1
16  
I/O1 – I/O8  
I/O9 – I/O16  
RAM Array  
1024 X 1024  
37  
36  
35  
34  
33  
I/O  
I/O  
8
A3  
2
3
9
A2  
A1  
A0  
14  
10  
11  
12  
13  
I/O  
V
SS  
I/O  
13  
4
CC  
V
SS  
V
V
CC  
I/O  
32  
I/O  
5
6
7
8
12  
31  
30  
29  
28  
I/O  
11  
I/O  
I/O  
9
I/O  
I/O  
I/O  
14  
15  
16  
10  
COLUMN DECODER  
WE 17  
NC  
18  
27  
26  
25  
A
A
8
15  
19  
A
A
14  
13  
9
10  
11  
BHE  
A
20  
21  
22  
A
A
WE  
CE  
OE  
A
12  
24  
23  
NC  
NC  
BLE  
62126BV–1  
62126BV–2  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose  
CA 95134  
408-943-2600  
June 14, 2000  

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