CXD2508AQ

更新时间： 2024-01-03 12:18:30

品牌	Logo	应用领域
索尼 - SONY		数字信号处理器
页数	文件大小	规格书
49页	856K
描述
CD Digital Signal Processor

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数据手册

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CXD2508AQ 数据手册

CXD2508AQ/AR

Pin No.

Symbol

AV^DD1

Description

I/O

Analog power supply for DSP.

EFM signal input.

36 RF

37 BIAS

38 ASYI

39 ASYO

40 ASYE

41 WDCK

42 LRCK

43 LRCKI

44 PCMD

45 PCMDI

46 BCK

Constant current input of asymmetry compensation circuit.

Comparator voltage input of asymmetry compensation circuit.

EFM full-swing output (low = Vss, high = VDD).

Low: asymmetry compensation off; high: asymmetry compensation on.

D/A interface for 48-bit slot. Word clock (2Fs).

D/A interface for 48-bit slot. LR clock (Fs).

LR clock input for DAC. (48-bit slot)

D/A interface. Serial data (two's complement, MSB first).

Audio data input for DAC. (48-bit slot)

D/A interface. Bit clock.

47 BCKI

48 GTOP

49 XUGF

50 XPCK

51 GFS

Bit clock input for DAC. (48-bit slot)

GTOP output.

XUGF output.

XPLCK output.

GFS output.

52 RFCK

RFCK output.

V^SS

GND.

54 C2PO

55 XROF

56 MNT3

57 MNT1

58 MNT0

59 FSTT

60 C4M

C2PO output.

XRAOF output.

MNT3 output.

MNT1 output.

MNT0 output.

2/3 frequency-divider output for Pins 73 and 74.

4.2336MHz output.

61 DOUT

Digital Out output.

Outputs high signal when the playback disc has emphasis, low signal when no

emphasis.

62 EMPH

63 EMPHI

64 WFCK

DAC de-emphasis on/off. High: on; low: off.

WFCK (write frame clock) output.

No-sound data detection output; high when no sound data is detected.

(Left channel)

65 ZEROL

No-sound data detection output; high when no sound data is detected.

(Right channel)

66 ZEROR

67 DTS1

Test pin 1 for DAC; normally low.

Digital power supply for DAC.

VDD

– 5 –

1 2 3 456 7 8...49

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