Definition of Terms
Load Regulation:
Dropout Voltage:
The input-output voltage differential at which the cir-
The change in output voltage for a change in load
cuit ceases to regulate against further reduction in
input voltage. Measured when the output voltage has
dropped 100mV from the nominal value obtained at
14V input, dropout voltage is dependent upon load
current and junction temperature.
current at constant chip temperature.
Quiescent Current:
The part of the positive input current that does not
contribute to the positive load current. The regulator
ground lead current.
Input Voltage:
Ripple Rejection:
The DC voltage applied to the input terminals with
respect to ground.
The ratio of the peak-to-peak input ripple voltage to
the peak-to-peak output ripple voltage.
Line Regulation:
Current Limit:
The change in output voltage for a change in the
input voltage. The measurement is made under con-
ditions of low dissipation or by using pulse tech-
niques such that the average chip temperature is not
significantly affected.
Peak current that can be delivered to the output.
Circuit Description
Capacitor temperature coefficient and tolerance as well as the
tolerance of the CS8151 must be taken into account in order
to get the correct system tolerance for each parameter.
Functional Description
To reduce the drain on the battery a system can go into a
low current consumption mode when ever its not per-
forming a main routine. The WAKE UP signal is generated
continuously and is used to interrupt a microcontroller
that is in sleep mode. The nominal output is a 5 volt
square wave with a duty cycle of 50% at a frequency that
WAKE UP
WDI
is determined by a timing capacitor, CDelay
.
When the microprocessor receives a rising edge from the
WAKE UP output, it must issue a watchdog pulse and
check its inputs to decide if it should resume normal oper-
ations or remain in the sleep mode.
The first falling edge of the watchdog signal causes the
WAKE UP to go low within 2µs (typ) and remain low until
the next WAKE UP cycle (see Figure 2). Other watchdog
pulses received within the same cycle are ignored (Figure
1).
WAKE UP
Response to
WDI
RESET
During power up,
is held low until the output volt-
Figure 2. WAKE UP response to WDI
age is in regulation. During operation, if the output volt-
age shifts below the regulation limits, the RESET toggles
low and remains low until proper output voltage regula-
tion is restored. After the
high.
______
RESET
RESET
RESET
returns
delay,
The WATCHDOG circuitry continuously monitors the
input watchdog signal (WDI) from the microprocessor.
The absence of a falling edge on the WATCHDOG input
RESET
during one WAKE UP cycle will cause a
occur at the end of the WAKE UP cycle. (see Figure 1b).
RESET
pulse to
WAKE UP
The WAKE UP output is pulled low during a
regardless of the cause of the . After the
RESET
RESET
returns high, the WAKE UP cycle begins again (see
Figures 1b).
The RESET pulse width, WAKE UP signal frequency and
WAKE UP
Response to
high to WAKE UP delay time are all set by one
RESET
external capacitor CDelay
______
RESET
.
WAKE UP period=(4x105)CDelay
Figure 3. WAKE UP response to
(Low Voltage)
RESET
4
RESET
RESET
Delay Time=(5x10 )CDelay
5
HIGH to WAKE UP Delay Time =(2x10 )CDelay
5
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