Myson/Century Inc.
CS6208
Embedded Network Microcontroller with 10/100 MAC and 10Mbs PHY
The CS6208 Embedded Network Microcontroller
is specifically targeted at applications that require
network access. It incorporates a high-speed 4-cycle/
instruction 8051 compatible microcontroller core
along with 65K bytes of on-chip program ROM
memory and 32K bytes of on-chip data SRAM.
External system memory is easily added to the
CS6208, with up to 131K bytes of code memory and
98K bytes data memory facilitating large programs.
CPU
• 4 cycle 80C51 instruction set compatible core.
• Programmable clock rate: DC/20MHz/40/60MHz.
• Single crystal operation.
• On-chip programmable PLL generates up to
60MHz processor clock.
• Two data pointers with auto-increment/decrement.
• Programmers model is 8051 compatible.
Memory Architecture
An on-chip crystal oscillator with programmable
PLL provides a simple yet robust clocking scheme.
• 65KB on-chip program memory: ROM
• 32KB on-chip SRAM usable as data or packet
buffer memory.
• Non-multiplexed external memory interface.
• External memory expansion up to 131K bytes
code and 98K bytes data.
Network access is facilitated by moving packets
through the transmit and receive buffers of the Media
Access Control (MAC) block. There is a 32K byte
packet buffer local to the MAC, shared with on-chip
data memory. The on-chip Ethernet Transceiver
allows direct connection to a twisted-pair network
environment. Other physical network media such as
Home PNA can be accessed by the 7-wire ENDEC
interface using external transceivers.
• In-system programming using external FLASH.
• Default memory map is 80C51 compatible.
Networking and I/O
• 10/100 Ethernet MAC with built-in Physical Layer,
single chip networking.
The CS6208 also includes the standard port 1 and
port 3 of the 8051. A full-duplex serial I/O port, 8
interrupt sources with three level priority, and 3 16-bit
timers are shared with these ports. In addition two 8-
bit wide programmable I/O ports are included for
external control applications. Two programmable
master/slave I2C interfaces are included for
communication with other hosts or slave devices
such as EEPROM.
• IEEE 802.3 7-wire ENDEC interface.
• 32KB on-chip TX/RX packet buffer memory
shared with CPU.
• Half-duplex MAC operation.
• Hardware checksum capability speeds network
protocol processing.
• Full-duplex serial port.
• Four 8-bit digital I/O ports, bi-directional.
Firmware
A four channel 7-Bit analog-to-digital converter
hold allows the CS6208 to interface directly with
analog circuits. Analog inputs can be converted
singly or in a round-robbin fashion using the A/D
input multiplexor.
• On chip HTTPD server.
• TCP/IP network stack accessible by application
programs.
• ARP, IP, ICMP, UDP, TCP, DHCP, and BOOTP
protocols implemented.
All functional blocks of the CS6208 can be
individually powered up/down to provide optimal
power management using the power config register.
An on-chip COP timer ensures reliable program
operation and the power-on/off detection circuit
keeps memory contents from being corrupted. The
CS6208 operates under a wide voltage range from
3.0V to 5.0V, and in low power mode the CPU core
can operate on only 1.8V.
Integrated System Resources
• High speed 7-bit analog-to-digital converter
• Programmable A/D clock rate.
• Two I2C interfaces both programmable for master
or slave operation.
• Three 16-bit on-chip timers.
• Eight interrupt sources with three priority levels.
• Full-Duplex UART.
Power Management
- 1 -
© 2002 Myson Century Semiconductor, Inc. All
rights reserved.
www.century-semi.com
www.myson.com.tw
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