Datasheet > CS5519CJI2FNTR-G1

CS5519CJI2FNTR-G1

更新时间： 2024-01-17 15:16:52

品牌	Logo	应用领域
美台 - DIODES		电信电信集成电路
页数	文件大小	规格书
17页	366K
描述
Telecom Circuit, 1-Func, 7 X 7 MM, GREEN, QFN-56

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技术参数
数据手册

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CS5519CJI2FNTR-G1 技术参数

是否Rohs认证：	符合	生命周期：	Active
包装说明：	7 X 7 MM, GREEN, QFN-56	Reach Compliance Code：	compliant
HTS代码：	8542.39.00.01	风险等级：	5.61
JESD-30 代码：	S-XQCC-N56	JESD-609代码：	e3
长度：	7 mm	湿度敏感等级：	3
功能数量：	1	端子数量：	56
最高工作温度：	85 °C	最低工作温度：	-40 °C
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	NOT SPECIFIED	座面最大高度：	0.8 mm
表面贴装：	YES	电信集成电路类型：	TELECOM CIRCUIT
温度等级：	INDUSTRIAL	端子面层：	Matte Tin (Sn)
端子形式：	NO LEAD	端子节距：	0.4 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	NOT SPECIFIED
宽度：	7 mm	Base Number Matches：	1

CS5519CJI2FNTR-G1 数据手册

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Data Sheet

Enhanced Multi-touch Capacitive Touch Screen Controller

CS5519

Pin Description

Pin Number

Pin Name

Pin Function

QFN-7×7

-56

QFN-8×8

Type

-68

Port 1.7 GPIO

8051 P1.7 GPIO

TXD1

This pin also can be configured as TXD of UART 1

P1.7/

TXD1/

PINT0.1

PINT0.1/

EXTCLKIN/

I/O

This pin also can be configured as the expanded INT0

interrupt

External Clock Input

External clock input source.

T0 Timer 0 Input

This pin also can be configured as Timer 0 input

Test Mode Enable High Active

This pin has an internal weakly pull low resistor

connected. If it is connected high, the chip enters into

Test Mode condition

TESTEN

Port 1.2 GPIO

8051 P1.2 GPIO

SDA

P1.2/SDA

(open-

drain)

I/O

This pin also can be configured as the SDA signal of

the I2C master or I2C slave controller. In this operation

mode, this pin should also be configured as

bi-directional I/O with open-drain output

Port 1.3 GPIO

8051 P1.3 GPIO

SCL

P1.3/SCL

(open-

drain)

I/O

This pin also can be configured as the SCL signal of

the I²C master or I²C slave controller. In I²C master

mode, this pin should be configured as open-drain

output. In I²C slave, this pin should be configured as

input only

Reset Low Active

Typically connect a resistor to VDD18 and a capacitor

to VSS

Low asserted and threshold at 0.5×V_DD18. When forced

low, the chip enters into reset condition

This pin should not be connected to any level above

V_DD18

RSTN

Apr. 2013 Rev. 1. 0

BCD Semiconductor Manufacturing Limited

1 2 345 6 7...17

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