CS44130

更新时间： 2024-02-21 05:13:20

品牌	Logo	应用领域
凌云 - CIRRUS		放大器
页数	文件大小	规格书
23页	330K
描述
60 W Quad Half-Bridge Digital Amplifier Power Stage

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CS44130 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Active	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	48
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	5.68
其他特性：	ALSO REQUIRES 10.8V TO 21V SUPPLY	内置保护：	TRANSIENT; OVER CURRENT
接口集成电路类型：	HB BASED PERIPHERAL DRIVER WITH PWM	JESD-30 代码：	S-XQCC-N48
JESD-609代码：	e3	长度：	9 mm
功能数量：	1	端子数量：	48
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出电流流向：	SOURCE AND SINK	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装形状：	SQUARE
封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE	峰值回流温度（摄氏度）：	260
认证状态：	Not Qualified	座面最大高度：	0.9 mm
最大供电电压：	3.47 V	最小供电电压：	3.14 V
标称供电电压：	3.3 V	电源电压1-最大：	5.25 V
电源电压1-分钟：	4.75 V	电源电压1-Nom：	5 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	MATTE TIN	端子形式：	NO LEAD
端子节距：	0.65 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	9 mm
Base Number Matches：	1

CS44130 数据手册

CS44130

5. RESET AND POWER-UP

Reliable power-up can be accomplished by keeping the device in reset until the power supplies, clocks, and

configuration pins are stable. It is also recommended that the RSTx/y pin be activated if the voltage supplies

drop below the recommended operating condition to prevent power-glitch- related issues.

When RSTx/y is low, the corresponding channels of the CS44130 enter a low-power mode and all internal

states are reset and the outputs are set to HI-Z. When RSTx/y is high, the desired mode settings will be

loaded and the outputs will begin normal operation.

5.1

PWM Popguard Transient Control

The CS44130 uses Popguard^®technology to minimize the effects of output transients during power-up

and power-down for half-bridge configurations. This technique reduces the audio transients commonly

produced by half-bridge, single-supply amplifiers when implemented with external DC-blocking capacitors

connected in series with the audio outputs.

When the device is configured for ramping (RAMP set high) and RSTx/y is set high and the inputs are

pulsed, the OUTx output will ramp-up to the bias point (VP/2). This gradual voltage ramping allows time

for the external DC-blocking capacitor to charge to the quiescent voltage, minimizing the power-up tran-

sient. The OUTx output will not begin normal operation until the ramp has reached the bias point. The INx

input must begin switching before the ramp cycle begins.

When the device is configured for ramping (RAMP set high) and RSTx/y is set low, the OUTx output will

begin to slowly ramp down from the bias point to PGND, allowing the DC-blocking capacitor to discharge.

It is not necessary to complete a ramp up/down sequence before ramping up/down again. PWM Popguard

should only be used in Half Bridge configurations.

5.2

Recommended Power-Up Sequence

1. Turn on the system power.

2. Hold RSTx/y low until the power supply and system clocks are stable. In this state, all associated

outputs are HI-Z.

3. Start the PWM modulator output.

4. Once the PWM modulator output is valid, release RSTx/y high. If the CS44130 is configured for

ramping, the outputs will ramp to the bias point and then begin switching normally. If the CS44130 is

not configured for ramping, the outputs will begin switching after approximately 35 cycles of the PWM

input signal.

5.3

Recommended Power-Down Sequence

1. Set RSTx/y low. If the CS44130 is configured for ramping, the outputs will ramp down to PGND and

then become HI-Z. If the CS44130 is not configured for ramping, the outputs will immediately become

HI-Z.

2. Power-down the remainder of the system.

3. Turn off the system power.

DS690PP1

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