P R O D U C T B R I E F
S1221
OC-3/12 SONET/SDH 8-bit Quad Transceiver
The S1221 performs SONET/SDH frame
Features
Description
detection.
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CMOS 0.13 micron technology
The S1221 SONET/SDH transceiver is one of the
latest additions to the AMCC product family.
The S1221 device provides fully integrated
serialization/de-serialization capabilities with
four independent transceivers. The device
performs all necessary parallel-to-serial and
serial-to-parallel functions in conformance with
the SONET/SDH transmission standards.
Complies with Bellcore and ITU-T specifica-
tions for jitter tolerance, jitter transfer, and jit-
ter generation
AMCC Suggested Interface Devices
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On-chip high-frequency PLLs for clock gener-
ation and clock recovery
Supports Data Rates for 155.52 Mbps (OC-3)
and 622.08 Mbps (OC-12)
8-bit LVCMOS Parallel data path
LVDS or LVPECL differential serial interface
Internal termination of the optic’s LVPECL
driver renders a seamless power saving con-
nection
Congo (S1201) POS/ATM SONET Mapper
Nile (S1202)
ATM SONET Mapper
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Orinoco (S1204) STS-12/STM-4 DS3/E3/STS-1E SONET/SDH Map-
per
Clock and Data Recovery are provided for the
standard operating rates of 155.52 Mbps (OC-3)
and 622.08 Mbps (OC-12).
Agilent
Finisar
HFBR-5908E, SFF Module
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Typical 715 mW power in LVDS I/O mode
Directly compatible with 2.5 V or 3.3 V LVDS,
3.3 V LVPECL (DC and AC)
FTRJ1322P1xTR, SFP Module
V23818-H18 SFF Module
The S1221 can also be provisioned to a mix and
match OC-3 and OC-12 data streams within the
same device.
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Frame and Byte Boundary Detection option
2
255 PBGA Package,17x17 mm with Green/
Sumitomo
OCP
SCP6802-GL, SFP Module SCM6005, SFF Module
TRPN03 & TRPN12, SFP Mod.
RoHS compliant lead free option
1.2 V and 3.3 V/2.5 V supply
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Receiver lock detect outputs
The S1221 can be configured in MII (Media
Independent Interface) mode (MII Mode) or in a
Non-MII mode.
Signal detect inputs
Selectable reference frequencies of 19.44,
77.76 or 155.52 MHz
JDS Uniphase
CT2-P, SFP Module
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Internal FIFO to decouple transmit clocks
Various diagnostic loopback modes
Quad configuration, mixed OC-3/OC-12
Built-In Self Test (BIST) Feature
Independent power down of unused channels
Drop-in-replacement for S1213
The figure below, System Block Diagram, shows
a typical network application.
The S1221 is divided into four transmitter
channels and four receiver channels.
Overview
The sequence of operations is as follows for
each Channel:
The S1221 can be used to implement the front
end of SONET/SDH equipment which consists
primarily of the serial transmit interface and the
serial receive interface. The Low Voltage LVDS or
LVPECL interfaces guarantee compliance with
the bit-error rate requirements of the Telcordia
and ITU-T standards.
Applications
Transmitter Operations
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SONET/SDH OC-3/OC-12
SONET/SDH modules
SONET/SDH test equipment
ATM over SONET/SDH
Section repeaters
Add Drop Multiplexers (ADM)
Broad-band cross-connects
Fiber optic terminators
Fiber optic test equipment
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8-bit parallel data input
Parallel-to-serial conversion
Serial data output
Receiver Operations For One Channel
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Serial data input
Clock and Data recovery
Serial-to-parallel data conversion
8-bit parallel data and clock output
The S1221 is divided into four Transceiver
modules with each possessing a clock recovery
unit. Each of the modules can run at OC-3 or
OC-12 data rates, independent of the other
modules.
Internal clocking and control functions are
transparent to the user.
S1221
S1221
8
8
8
DATA
DATA
DATA
DATA
DATA
DATA
ORX
Framer
Or
ASIC
Framer
Or
ASIC
OTX
CLOCK
CLOCK
8
8
8
8
DATA
DATA
ORX
OTX
CLOCK
CLOCK
8
DATA
DATA
DATA
DATA
DATA
DATA
ORX
OTX
Framer
Or
Framer
Or
CLOCK
CLOCK
ORX
DATA
OTX
DATA
ASIC
ASIC
CLOCK
CLOCK
8
8
8
8
DATA
DATA
Framer
Or
ASIC
Framer
Or
ASIC
CLOCK
CLOCK
DATA
DATA
DATA
DATA
DATA
DATA
ORX
OTX
8
8
8
8
DATA
DATA
CLOCK
CLOCK
ORX
OTX
DATA
DATA
DATA
DATA
CLOCK
CLOCK
Framer
Or
ASIC
ORX
Framer
Or
ASIC
OTX
DATA
DATA
ORX
OTX
CLOCK
CLOCK
MII port
MII port
System Block Diagram with the S1221
5秒后页面跳转
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