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CP82C89Z PDF预览

CP82C89Z

更新时间: 2024-02-25 06:19:10
品牌 Logo 应用领域
英特矽尔 - INTERSIL 外围集成电路光电二极管时钟
页数 文件大小 规格书
13页 317K
描述
CMOS Bus Arbiter

CP82C89Z 技术参数

是否无铅:不含铅是否Rohs认证:符合
生命周期:Obsolete零件包装代码:DIP
包装说明:DIP, DIP20,.3针数:20
Reach Compliance Code:compliant风险等级:5.11
Is Samacsys:N总线兼容性:8089; 80C88; 8088; 80C86; 8086
最大时钟频率:8 MHzJESD-30 代码:R-PDIP-T20
JESD-609代码:e3长度:25.895 mm
端子数量:20最高工作温度:70 °C
最低工作温度:封装主体材料:PLASTIC/EPOXY
封装代码:DIP封装等效代码:DIP20,.3
封装形状:RECTANGULAR封装形式:IN-LINE
峰值回流温度(摄氏度):NOT APPLICABLE电源:5 V
认证状态:Not Qualified座面最大高度:5.33 mm
子类别:System Interface Logic ICs最大供电电压:5.5 V
最小供电电压:4.5 V标称供电电压:5 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子面层:Matte Tin (Sn) - annealed
端子形式:THROUGH-HOLE端子节距:2.54 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT APPLICABLE
宽度:7.62 mmuPs/uCs/外围集成电路类型:SYSTEM INTERFACE LOGIC, BUS ARBITER AND CONTINUOUS SIGNAL GENERATOR
Base Number Matches:1

CP82C89Z 数据手册

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82C89  
The IOB strapping option configures the 82C89 Bus Arbiter  
into the IOB mode and the strapping option RESB  
configures it into the RESB mode. It might be noted at this  
point that if both strapping options are strapped false, the  
arbiter interfaces the processor to a multi-master system bus  
only (see Figure 4). With both options strapped true, the  
arbiter interfaces the processor to a multi-master system  
bus, a Resident Bus, and an I/O Bus.  
Which Priority Resolving Technique To Use  
There are advantages and disadvantages for each of the  
techniques described above. The rotating priority resolving  
technique requires substantial external logic to implement  
while the serial technique uses no external logic but can  
accommodate only a limited number of bus arbiters before the  
daisy-chain propagation delay exceeds the multimaster’s  
system bus clock (BCLK). The parallel priority resolving  
technique is in general a good compromise between the other  
two techniques. It allows for many arbiters to be present on  
the bus while not requiring too much logic to implement.  
In the IOB mode, the processor communicates and controls  
a host of peripherals over the Peripheral Bus. When the I/O  
Processor needs to communicate with system memory, it  
does so over the system memory bus. Figure 5 shows a  
possible I/O Processor system configuration.  
82C89 Modes Of Operation  
There are two types of processors for which the 82C89 will  
provide support: An Input/Output processor (i.e. an NMOS  
8089 IOP) and the 80C86, 80C88. Consequently, there are  
two basic operating modes in the 82C89 bus arbiter. One,  
the IOB (I/O Peripheral Bus) mode, permits the processor  
access to both an I/O Peripheral Bus and a multi-master  
system bus. The second, the RESB (Resident Bus mode),  
permits the processor to communicate over both a Resident  
Bus and a multi-master system bus. An I/O Peripheral Bus is  
a bus where all devices on that bus, including memory, are  
treated as I/O devices and are addressed by I/O commands.  
All memory commands are directed to another bus, the  
multi-master system bus. A Resident Bus can issue both  
memory and I/O commands, but it is a distinct and separate  
bus from the multi-master system bus. The distinction is that  
the Resident Bus has only one master, providing full  
The 80C86 and 80C88 processors can communicate with a  
Resident Bus and a multi-master system bus. Two bus  
controllers and only one Bus Arbiter would be needed in  
such a configuration as shown in Figure 6. In such a system  
configuration the processor would have access to memory  
and peripherals of both busses. Memory mapping  
techniques are applied to select which bus is to be  
accessed. The SYSB/RESB input on the arbiter serves to  
instruct the arbiter as to whether or not the system bus is to  
be accessed. The signal connected to SYSB/RESB also  
enables or disables commands from one of the bus  
controllers. A summary of the modes that the 82C89 has,  
along with its response to its status lines inputs, is shown in  
Table 1.  
availability and being dedicated to that one master.  
FN2980.2  
5
February 27, 2006  

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