Datasheet > CP82C88-10

CP82C88-10

更新时间： 2024-01-29 01:03:54

品牌	Logo	应用领域
英特矽尔 - INTERSIL		总线控制器外围集成电路光电二极管时钟
页数	文件大小	规格书
10页	133K
描述
CMOS Bus Controller

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技术参数
数据手册
替代型号

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CP82C88-10 技术参数

是否Rohs认证：	不符合	生命周期：	Obsolete
包装说明：	DIP, DIP20,.3	Reach Compliance Code：	unknown
风险等级：	5.07	总线兼容性：	80188; 80186; 8089; 80C88; 8088; 80C86; 8086
最大时钟频率：	10 MHz	JESD-30 代码：	R-PDIP-T20
JESD-609代码：	e0	端子数量：	20
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP20,.3	封装形状：	RECTANGULAR
封装形式：	IN-LINE	峰值回流温度（摄氏度）：	NOT SPECIFIED
电源：	5 V	认证状态：	Not Qualified
子类别：	Bus Controllers	最大压摆率：	10 mA
最大供电电压：	5.5 V	最小供电电压：	4.5 V
标称供电电压：	5 V	表面贴装：	NO
技术：	CMOS	温度等级：	COMMERCIAL
端子面层：	Tin/Lead (Sn/Pb)	端子形式：	THROUGH-HOLE
端子节距：	2.54 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	NOT SPECIFIED	uPs/uCs/外围集成电路类型：	SYSTEM INTERFACE LOGIC, CONTROL AND COMMAND SIGNAL GENERATOR
Base Number Matches：	1

CP82C88-10 数据手册

82C88

INTA (Interrupt Acknowledge) acts as an I/O read during an Interrupt Acknowledge and MCE

interrupt cycle. Its purpose is to inform an interrupting device

that its interrupt is being acknowledged and that it should

place vectoring information onto the data bus.

The MCE signal is used during an interrupt acknowledge

cycle if the 82C88 is in the System Bus mode (IOB LOW).

During any interrupt sequence, there are two interrupt

acknowledge cycles that occur back to back. During the ﬁrst

interrupt cycle no data or address transfers take place. Logic

should be provided to mask off MCE during this cycle. Just

before the second cycle begins the MCE signal gates a mas-

ter Priority Interrupt Controller’s (PIC) cascade address onto

the processor’s local bus where ALE (Address Latch Enable)

strobes it into the address latches. On the leading edge of

the second interrupt cycle, the addressed slave PIC gates an

interrupt vector onto the system data bus where it is read by

the processor.

The command outputs are:

MRDC - Memory Read Command

MWTC - Memory Write Command

IORC - I/O Read Command

IOWC - I/O Write Command

AMWC - Advanced Memory Write Command

AIOWC - Advanced I/O Write Command

INTA - Interrupt Acknowledge

If the system contains only one PIC, the MCE signal is not

used. In this case, the second Interrupt Acknowledge signal

gates the interrupt vector onto the processor bus.

Control Outputs

The control outputs of the 82C88 are Data Enable (DEN),

Data Transmit/Receive (DT/R) and Master Cascade Enable/ Address Latch Enable and Halt

Peripheral Data Enable (MCE/PDEN). The DEN signal

Address Latch Enable (ALE) occurs during each machine

determines when the external bus should be enabled onto

the local bus and the DT/R determines the direction of data

transfer. These two signals usually go to the chip select and

direction pins of a transceiver.

cycle and serves to strobe the current address into the

82C82/82C83H address latches. ALE also serves to strobe

the status (S0, S1, S2) into a latch for halt state decoding.

Command Enable

The MCE/PDEN pin changes function with the two modes of

the 82C88. When the 82C88 is in the IOB mode (IOB HIGH),

the PDEN signal serves as a dedicated data enable signal

for the I/O or Peripheral System bus.

The Command Enable (CEN) input acts as a command

qualiﬁer for the 82C88. If the CEN pin is high, the 82C88

functions normally. If the CEN pin is pulled LOW, all com-

mand lines are held in their inactive state (not three-state).

This feature can be used to implement memory partitioning

and to eliminate address conﬂicts between system bus

devices and resident bus devices.

4-336

1 2 345 6 7...10

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CP82C88-10 替代型号

型号	品牌	替代类型	描述	数据表
D82C288-8	AMD	功能相似	Bus Controller for iAPX 286 Processors
CP82C89	INTERSIL	功能相似	CMOS Bus Arbiter

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