Datasheet > CP82C59AZ

CP82C59AZ

更新时间： 2024-02-19 09:17:35

品牌	Logo	应用领域
英特矽尔 - INTERSIL		中断控制器
页数	文件大小	规格书
22页	410K
描述
CMOS Priority Interrupt Controller

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技术参数
数据手册

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CP82C59AZ 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	DIP
包装说明：	DIP, DIP28,.6	针数：	28
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	风险等级：	7.54
总线兼容性：	80C86; 80C88; 80C286; 8080; 8085; 8086; 8088; 80286; NSC800	外部数据总线宽度：	8
JESD-30 代码：	R-PDIP-T28	JESD-609代码：	e3
长度：	37.4 mm	外部中断装置数量：	8
端子数量：	28	最高工作温度：	70 °C
最低工作温度：		封装主体材料：	PLASTIC/EPOXY
封装代码：	DIP	封装等效代码：	DIP28,.6
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT APPLICABLE	电源：	5 V
认证状态：	Not Qualified	座面最大高度：	6.35 mm
子类别：	Interrupt Controllers	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT APPLICABLE
宽度：	15.24 mm	uPs/uCs/外围集成电路类型：	INTERRUPT CONTROLLER
Base Number Matches：	1

CP82C59AZ 数据手册

82C59A

Interrupt Request Register (IRR) and In-Service Register

Read (RD)

(ISR)

A LOW on this input enables the 82C59A to send the status

of the Interrupt Request Register (lRR), In-Service Register

(lSR), the Interrupt Mask Register (lMR), or the interrupt

level (in the poll mode) onto the Data Bus.

The interrupts at the IR input lines are handled by two registers

in cascade, the Interrupt Request Register (lRR) and the In-

Service Register (lSR). The IRR is used to indicate all the

interrupt levels which are requesting service, and the ISR is

used to store all the interrupt levels which are currently being

serviced.

This input signal is used in conjunction with WR and RD

signals to write commands into the various command

registers, as well as to read the various status registers of

the chip. This line can be tied directly to one of the system

address lines.

Priority Resolver

This logic block determines the priorities of the bits set in the

lRR. The highest priority is selected and strobed into the

corresponding bit of the lSR during the INTA sequence.

The Cascade Buffer/Comparator

Interrupt Mask Register (IMR)

This function block stores and compares the IDs of all

82C59As used in the system. The associated three I/O pins

(CAS0 - 2) are outputs when the 82C59A is used as a

master and are inputs when the 82C59A is used as a slave.

As a master, the 82C59A sends the ID of the interrupting

slave device onto the CAS0 - 2 lines. The slave, thus

selected will send its preprogrammed subroutine address

onto the Data Bus during the next one or two consecutive

INTA pulses. (See section “Cascading the 82C59A”.)

The lMR stores the bits which disable the interrupt lines to be

masked. The IMR operates on the output of the IRR.

Masking of a higher priority input will not affect the interrupt

request lines of lower priority.

Interrupt (INT)

This output goes directly to the CPU interrupt input. The

VOH level on this line is designed to be fully compatible with

the 8080, 8085, 8086/88, 80C86/88, 80286, and 80C286

input levels.

Interrupt Sequence

The powerful features of the 82C59A in a microcomputer

system are its programmability and the interrupt routine

addressing capability. The latter allows direct or indirect

jumping to the specified interrupt routine requested without

any polling of the interrupting devices. The normal sequence

of events during an interrupt depends on the type of CPU

being used.

Interrupt Acknowledge (INTA)

INTA pulses will cause the 82C59A to release vectoring

information onto the data bus. The format of this data

depends on the system mode (µPM) of the 82C59A.

Data Bus Buffer

This 3-state, bidirectional 8-bit buffer is used to interface the

82C59A to the System Data Bus. Control words and status

information are transferred through the Data Bus Buffer.

Read/Write Control Logic

The function of this block is to accept output commands from

the CPU. It contains the Initialization Command Word (lCW)

registers and Operation Command Word (OCW) registers

which store the various control formats for device operation.

This function block also allows the status of the 82C59A to

be transferred onto the Data Bus.

Chip Select (CS)

A LOW on this input enables the 82C59A. No reading or

writing of the device will occur unless the device is selected.

Write (WR)

A LOW on this input enables the CPU to write control words

(lCWs and OCWs) to the 82C59A.

FN2784.5

March 17, 2006

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