Datasheet > CP82C59A-5

CP82C59A-5

更新时间： 2024-02-16 08:53:20

品牌	Logo	应用领域
英特矽尔 - INTERSIL		中断控制器
页数	文件大小	规格书
20页	155K
描述
CMOS Priority Interrupt Controller

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技术参数
数据手册

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CP82C59A-5 技术参数

是否Rohs认证：	不符合	生命周期：	Transferred
包装说明：	DIP, DIP28,.6	Reach Compliance Code：	unknown
风险等级：	5.63	总线兼容性：	80C86; 80C88; 80C286; 8080; 8085; 8086; 8088; 80286; NSC800
最大时钟频率：	5 MHz	外部数据总线宽度：	8
JESD-30 代码：	R-PDIP-T28	JESD-609代码：	e0
外部中断装置数量：	8	端子数量：	28
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装等效代码：	DIP28,.6	封装形状：	RECTANGULAR
封装形式：	IN-LINE	电源：	5 V
认证状态：	Not Qualified	子类别：	Interrupt Controllers
最大压摆率：	5 mA	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Tin/Lead (Sn/Pb)
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	uPs/uCs/外围集成电路类型：	INTERRUPT CONTROLLER
Base Number Matches：	1

CP82C59A-5 数据手册

82C59A

Pin Description

SYMBOL

NUMBER

TYPE

DESCRIPTION

: The +5V power supply pin. A 0.1µF capacitor between pins 28 and 14 is recommended for

decoupling.

GND

GROUND

CHIP SELECT: A low on this pin enables RD and WR communications between the CPU and the

82C59A. INTA functions are independent of CS.

WRITE: A low on this pin when CS is low enables the 82C59A to accept command words from

the CPU.

READ: A low on this pin when CS is low enables the 82C59A to release status onto the data bus

for the CPU.

D7 - D0

4 - 11

I/O

BIDIRECTIONAL DATA BUS: Control, status, and interrupt-vector information is transferred via

this bus.

CAS0 - CAS2 12, 13, 15

CASCADE LINES: The CAS lines form a private 82C59A bus to control a multiple 82C59A struc-

ture. These pins are outputs for a master 82C59A and inputs for a slave 82C59A.

SP/EN

SLAVE PROGRAM/ENABLE BUFFER: This is a dual function pin. When in the Buffered Mode it

can be used as an output to control buffer transceivers (EN). When not in the Buffered Mode it is

used as an input to designate a master (SP = 1) or slave (SP = 0).

INT

INTERRUPT: This pin goes high whenever a valid interrupt request is asserted. It is used to inter-

rupt the CPU, thus, it is connected to the CPU's interrupt pin.

IR0 - IR7

18 - 25

INTERRUPT REQUESTS: Asynchronous inputs. An interrupt request is executed by raising an

IR input (low to high), and holding it high until it is acknowledged (Edge Triggered Mode), or just

by a high level on an IR input (Level Triggered Mode). Internal pull-up resistors are implemented

on IR0 - 7.

INTA

INTERRUPT ACKNOWLEDGE: This pin is used to enable 82C59A interrupt-vector data onto the

data bus by a sequence of interrupt acknowledge pulses issued by the CPU.

ADDRESS LINE: This pin acts in conjunction with the CS, WR, and RD pins. It is used by the

82C59A to decipher various Command Words the CPU writes and status the CPU wishes to read.

It is typically connected to the CPU A0 address line (A1 for 80C86/88/286).

Functional Description

CPU - DRIVEN

MULTIPLEXER

Interrupts in Microcomputer Systems

CPU

Microcomputer system design requires that I/O devices such

as keyboards, displays, sensors and other components

receive servicing in an efﬁcient manner so that large

amounts of the total system tasks can be assumed by the

microcomputer with little or no effect on throughput.

RAM

ROM

I/O (1)

I/O (2)

The most common method of servicing such devices is the

Polled approach. This is where the processor must test each

device in sequence and in effect “ask” each one if it needs

servicing. It is easy to see that a large portion of the main

program is looping through this continuous polling cycle and

that such a method would have a serious, detrimental effect

on system throughput, thus, limiting the tasks that could be

assumed by the microcomputer and reducing the cost effec-

tiveness of using such devices.

I/O (N)

FIGURE 2. POLLED METHOD

4-3

1 234 5 6 7...20

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