Datasheet > CP82C54Z

CP82C54Z

更新时间： 2024-02-03 03:17:06

品牌	Logo	应用领域
英特矽尔 - INTERSIL		外围集成电路光电二极管双倍数据速率时钟
页数	文件大小	规格书
22页	387K
描述
CMOS Programmable Intervel Timer

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CP82C54Z 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Transferred	零件包装代码：	DIP
包装说明：	DIP,	针数：	24
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	11 weeks
风险等级：	3.37	最大时钟频率：	8 MHz
外部数据总线宽度：	8	信息访问方法：	PARALLEL, DIRECT ADDRESS
JESD-30 代码：	R-PDIP-T24	JESD-609代码：	e3
长度：	31 mm	位数：	16
端子数量：	24	计时器数量：	3
最高工作温度：	70 °C	最低工作温度：
封装主体材料：	PLASTIC/EPOXY	封装代码：	DIP
封装形状：	RECTANGULAR	封装形式：	IN-LINE
峰值回流温度（摄氏度）：	NOT APPLICABLE	认证状态：	Not Qualified
座面最大高度：	6.35 mm	最大供电电压：	5.5 V
最小供电电压：	4.5 V	标称供电电压：	5 V
表面贴装：	NO	技术：	CMOS
温度等级：	COMMERCIAL	端子面层：	Matte Tin (Sn) - annealed
端子形式：	THROUGH-HOLE	端子节距：	2.54 mm
端子位置：	DUAL	处于峰值回流温度下的最长时间：	NOT APPLICABLE
宽度：	15.24 mm	uPs/uCs/外围集成电路类型：	TIMER, PROGRAMMABLE
Base Number Matches：	1

CP82C54Z 数据手册

82C54

The status register, shown in the figure, when latched,

contains the current contents of the Control Word Register

and status of the output and null count flag. (See detailed

explanation of the Read-Back command.)

82C54 System Interface

The 82C54 is treated by the system software as an array of

peripheral I/O ports; three are counters and the fourth is a

control register for MODE programming.

The actual counter is labeled CE (for Counting Element). It is

a 16-bit presettable synchronous down counter.

Basically, the select inputs A0, A1 connect to the A0, A1

address bus signals of the CPU. The CS can be derived

directly from the address bus using a linear select method or

it can be connected to the output of a decoder.

INTERNAL BUS

Operational Description

CONTROL

WORD

STATUS

LATCH

General

After power-up, the state of the 82C54 is undefined. The

Mode, count value, and output of all Counters are undefined.

STATUS

How each Counter operates is determined when it is

programmed. Each Counter must be programmed before it

can be used. Unused counters need not be programmed.

CONTROL

LOGIC

Programming the 82C54

Counters are programmed by writing a Control Word and

then an initial count.

All Control Words are written into the Control Word Register,

which is selected when A1, A0 = 11. The Control Word

specifies which Counter is being programmed.

GATE n

CLK n OUT n

FIGURE 3. COUNTER INTERNAL BLOCK DIAGRAM

By contrast, initial counts are written into the Counters, not

the Control Word Register. The A1, A0 inputs are used to

select the Counter to be written into. The format of the initial

count is determined by the Control Word used.

OLM and OLL are two 8-bit latches. OL stands for “Output

Latch”; the subscripts M and L for “Most significant byte” and

“Least significant byte”, respectively. Both are normally referred

to as one unit and called just OL. These latches normally

“follow” the CE, but if a suitable Counter Latch Command is

sent to the 82C54, the latches “latch” the present count until

read by the CPU and then return to “following” the CE. One

latch at a time is enabled by the counter’s Control Logic to drive

the internal bus. This is how the 16-bit Counter communicates

over the 8-bit internal bus. Note that the CE itself cannot be

read; whenever you read the count, it is the OL that is being

read.

ADDRESS BUS (16)

A1 A0

CONTROL BUS

I/OR I/OW

DATA BUS (8)

D0 - D7

82C54

COUNTER

Similarly, there are two 8-bit registers called CRM and CRL (for

“Count Register”). Both are normally referred to as one unit and

called just CR. When a new count is written to the Counter, the

count is stored in the CR and later transferred to the CE. The

Control Logic allows one register at a time to be loaded from

the internal bus. Both bytes are transferred to the CE

simultaneously. CRM and CRL are cleared when the Counter is

programmed for one byte counts (either most significant byte

only or least significant byte only) the other byte will be zero.

Note that the CE cannot be written into; whenever a count is

written, it is written into the CR.

OUTGATE CLK OUTGATE CLK OUTGATE CLK

FIGURE 4. COUNTER INTERNAL BLOCK DIAGRAM

Write Operations

The programming procedure for the 82C54 is very flexible.

Only two conventions need to be remembered:

1. For Each Counter, the Control Word must be written

before the initial count is written.

The Control Logic is also shown in the diagram. CLK n,

GATE n, and OUT n are all connected to the outside world

through the Control Logic.

2. The initial count must follow the count format specified in the

Control Word (least significant byte only, most significant

byte only, or least significant byte and then most significant

byte).

1...4 5 678 9 10...22

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