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CLC532AJP

更新时间： 2024-01-28 23:57:33
品牌 Logo 应用领域
美国国家半导体 - NSC 复用器开关复用器或开关信号电路光电二极管
页数 文件大小 规格书
12页 280K
描述
High-Speed 2:1 Analog Multiplexer

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CLC532AJP 技术参数

生命周期：Obsolete包装说明：DIE,
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.65模拟集成电路 - 其他类型：SINGLE-ENDED MULTIPLEXER
JESD-30 代码：X-XUUC-N14标称负供电电压 (Vsup)：-5.2 V
信道数量：2功能数量：1
端子数量：14标称断态隔离度：80 dB
封装主体材料：UNSPECIFIED封装代码：DIE
封装形状：UNSPECIFIED封装形式：UNCASED CHIP
认证状态：Not Qualified标称供电电压 (Vsup)：5 V
表面贴装：YES最长断开时间：7 ns
最长接通时间：20 ns技术：BIPOLAR
端子形式：NO LEAD端子位置：UPPER
Base Number Matches：1

CLC532AJP 数据手册

 浏览型号CLC532AJP的Datasheet PDF文件第3页浏览型号CLC532AJP的Datasheet PDF文件第4页浏览型号CLC532AJP的Datasheet PDF文件第5页浏览型号CLC532AJP的Datasheet PDF文件第7页浏览型号CLC532AJP的Datasheet PDF文件第8页浏览型号CLC532AJP的Datasheet PDF文件第9页 
Applications Information  
Operation  
CLC532  
6
The CLC532 is a 2:1 analog multiplexer with high-impedance  
buffered inputs, and a low-impedance, low-distortion, output  
stage. The CLC532 employs a closed-loop design, which  
dramatically improves accuracy. The channel SELECT control  
(Figure 1) determines which of the two inputs (INA or INB) is  
present at the OUTPUT. Beyond the basic multiplexer function,  
the CLC532 offers compatibility with either TTL or ECL logic  
families, as well as adjustable bandwidth.  
TTL CMOS  
620Ω 3.6kΩ  
200Ω 510Ω  
510Ω 680Ω  
D
REF  
+5V  
R3  
R2  
R1  
7
+5V  
R3  
R1  
CHANNEL  
SELECT  
R2  
A B  
/
+5V  
Figure 3: TTL/CMOS Level Channel SELECT Configuration  
+6.8µF  
Compensation  
µ
The CLC532 incorporates compensation nodes that allow both  
its bandwidth and its settling time/slew rate to be adjusted.  
Bandwidth and settling time/slew adjustments are linked,  
meaning that lowering the bandwidth also lowers slew rate  
and lengthens settling time. Proper adjustment (compensation)  
is necessary to optimize system performance. Time Domain  
applications should generally be optimized for lowest RMS  
noise at the CLC532 output, while maintaining settling time and  
slew rates at adequate levels to meet system needs. Frequency  
Domainapplicationsshouldgenerallybeoptimizedformaximally  
flat frequency response.  
0.1  
F
CHANNEL A  
CCOMP  
1
2
1
INA  
13  
14  
RIN  
12  
10  
11  
VOUT  
CLC532  
6
RL  
CHANNEL B  
4
3
DREF  
9
INB  
8
7
5
CCOMP  
RIN  
2
DGND  
Figure 4 below describes the basic relationship between  
bandwidth and RS for various values of load capacitance, CL,  
where CCOMP = 10pF.  
+6.8µF  
0.1µF  
CHANNEL  
SELECT  
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
100  
90  
80  
70  
60  
50  
40  
30  
20  
10  
0
R
s
CL  
1kΩ  
-5.2V  
2V Output Step  
Rs  
Figure 1: Standard CLC532 Circuit Configuration  
Digital Interface and Channel SELECT  
The CLC532 functions with ECL, TTL and CMOS logic families.  
REF controls logic compatibility. In normal operation, DREF is left  
0.01%  
Ts  
D
0.05%  
floating, and the channel SELECT responds to ECL level signals,  
Figure 2. For TTL or CMOS level SELECT inputs (Figure 3), DREF  
should be tied to +5V (the CLC532 incorporates an internal  
2300Ω series isolation resistor for the DREF input). For TTL or  
CMOS operation, the channel SELECT requires a resistor input  
network to prevent saturation of the channel select circuitry.  
Without this input network, channel SELECT logic levels above  
3V will cause internal junction saturation and slow switching  
speeds.  
1
100  
CL (pF)  
1000  
Figure 4: Settling Time and RS vs. CL  
Figure 5 shows the resulting changes in bandwidth and slew rate  
for increasing values of CCOMP . The RMS noise at the CLC532  
output can be approximated as:  
OUTPUTNOISE  
= (nV)(√1.57*BW-3dB)  
RMS  
CLC532  
where... nV = input spot noise voltage;  
BW-3dB = Bandwidth is from figure 5.  
6
DREF  
7
(NC)  
200  
180  
160  
140  
200  
180  
160  
140  
120  
100  
80  
SELECT  
ECL GATE  
Thevinen Equivalent  
Output Termination  
CHANNEL  
SELECT  
120  
Slew Rate  
A
/B  
100  
80  
R1  
81Ω  
50Ω  
50Ω  
To ECL  
Gate  
To  
SELECT  
60  
60  
-3dB Bandwidth  
40  
-2V  
40  
R2 130  
Ω
20  
0
20  
-5.2V  
1
10  
100  
Ccomp (pF)  
Figure 2: ECL Level Channel SELECT Configuration  
Figure 5: CCOMP for Maximally Flat Frequency Response  
http://www.national.com  
6
1...3456789...12

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