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CLC031AVEC

更新时间： 2024-02-15 14:32:14
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摩托罗拉 - MOTOROLA 商用集成电路先进先出芯片
页数 文件大小 规格书
31页 394K
描述
SMPTE 292M/259M Digital Video Deserializer / Descrambler with Video and Ancillary Data FIFOs

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CLC031AVEC 技术参数

是否无铅： 含铅是否Rohs认证： 不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TFQFP, TQFP64,.47SQ针数：64
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.74Is Samacsys：N
商用集成电路类型：CONSUMER CIRCUITJESD-30 代码：S-PQFP-G64
JESD-609代码：e0长度：10 mm
湿度敏感等级：2功能数量：1
端子数量：64最高工作温度：70 °C
最低工作温度：封装主体材料：PLASTIC/EPOXY
封装代码：TFQFP封装等效代码：TQFP64,.47SQ
封装形状：SQUARE封装形式：FLATPACK, THIN PROFILE, FINE PITCH
峰值回流温度（摄氏度）：235电源：2.5,3.3 V
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Other Consumer ICs最大供电电压 (Vsup)：2.625 V
最小供电电压 (Vsup)：2.375 V表面贴装：YES
技术：BICMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn85Pb15)端子形式：GULL WING
端子节距：0.5 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：10 mm
Base Number Matches：1

CLC031AVEC 数据手册

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September 2004  
CLC031A  
SMPTE 292M/259M Digital Video Deserializer /  
Descrambler with Video and Ancillary Data FIFOs  
The CLC031A’s internal circuitry is powered from +2.5 Volts  
and the I/O circuitry from a +3.3 Volt supply. Power dissipa-  
tion is typically 850mW. The device is packaged in a 64-pin  
TQFP.  
General Description  
The CLC031A SMPTE 292M  
/ 259M Digital Video  
Deserializer/Descrambler with Video and Ancillary Data  
FIFOs is a monolithic integrated circuit that deserializes and  
decodes SMPTE 292M, 1.485Gbps (or 1.483Gbps) serial  
component video data, to 20-bit parallel data with a synchro-  
nized parallel word-rate clock. It also deserializes and de-  
Features  
n SDTV/HDTV serial digital video standard compliant  
n Supports 270 Mbps, 360 Mbps, 540 Mbps, 1.483 Gbps  
and 1.485 Gbps serial video data rates with  
auto-detection  
codes  
SMPTE  
259M,  
270Mbps,  
360Mbps  
and  
SMPTE 344M (proposed) 540Mbps serial component video  
data, to 10-bit parallel data. Functions performed by the  
CLC031A include: clock/data recovery from the serial data,  
serial-to-parallel data conversion, SMPTE standard data de-  
coding, NRZI-to-NRZ conversion, parallel data clock genera-  
tion, word framing, CRC and EDH data checking and han-  
dling, Ancillary Data extraction and automatic video format  
determination. The parallel video output features a variable-  
depth FIFO which can be adjusted to delay the output data  
up to 4 parallel data clock periods. Ancillary Data may be  
selectively extracted from the parallel data through the use  
of masking and control bits in the configuration and control  
registers and stored in the on-chip FIFO. Reverse LSB dith-  
ering is also implemented.  
n LSB de-dithering option  
n Uses low-cost 27MHz crystal or clock oscillator  
reference  
<
n Fast VCO lock time: 500 µs at 1.485 Gbps  
n Built-in self-test (BIST) and video test pattern generator  
(TPG)*  
n Automatic EDH/CRC word and flag processing  
n Ancillary Data FIFO with extensive packet handling  
options  
n Adjustable, 4-deep parallel output video data FIFO  
n Flexible control and configuration I/O port  
n LVCMOS compatible control inputs and clock and data  
outputs  
n LVDS and ECL-compatible, differential, serial inputs  
n 3.3V I/O power supply and 2.5V logic power supply  
operation  
The unique multi-functional I/O port of the CLC031A pro-  
vides external access to functions and data stored in the  
configuration and control registers. This feature allows the  
designer greater flexibility in tailoring the CLC031A to the  
desired application. The CLC031A is auto-configured to a  
default operating condition at power-on or after a reset com-  
mand. Separate power pins for the PLL, deserializer and  
other functional circuits improve power supply rejection and  
noise performance.  
n Low power: typically 850mW  
n 64-pin TQFP package  
n Commercial temperature range 0˚C to +70˚C  
* Patent applications made or pending.  
The CLC031A has a unique Built-In Self-Test (BIST) and  
video Test Pattern Generator (TPG). The BIST enables com-  
prehensive testing of the device by the user. The BIST uses  
the TPG as input data and includes SD and HD component  
video test patterns, reference black, PLL and EQ pathologi-  
cals and a 75% saturation, 8 vertical colour bar pattern, for  
all implemented rasters. The colour bar pattern has optional  
transition coding at changes in the chroma and luma bar  
data. The TPG data is output via the parallel data port.  
Applications  
n SDTV/HDTV serial-to-parallel digital video interfaces for:  
— Video editing equipment  
— VTRs  
— Standards converters  
— Digital video routers and switchers  
— Digital video processing and editing equipment  
— Video test pattern generators and digital video test  
equipment  
The CLC030, SMPTE 292M / 259M Digital Video Serializer  
with Ancillary Data FIFO and Integrated Cable Driver, is the  
ideal complement to the CLC031A.  
— Video signal generators  
Ordering Information  
Order Number  
Package Type  
64-Pin TQFP  
NS Package Number  
CLC031AVEC  
VEC-64A  
© 2004 National Semiconductor Corporation  
DS200201  
www.national.com  
1234567...31

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