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CHL8325A-00CRT PDF预览

CHL8325A-00CRT

更新时间: 2024-09-24 12:43:19
品牌 Logo 应用领域
英飞凌 - INFINEON 多相元件控制器
页数 文件大小 规格书
3页 390K
描述
Digital Multi-Phase Buck Controller Dual OCP support for I-spike enhanced AMD CPUs

CHL8325A-00CRT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:5.81Base Number Matches:1

CHL8325A-00CRT 数据手册

 浏览型号CHL8325A-00CRT的Datasheet PDF文件第2页浏览型号CHL8325A-00CRT的Datasheet PDF文件第3页 
IR3541  
CHL8325A/B  
Digital Multi-Phase Buck Controller  
FEATURES  
DESCRIPTION  
5-phase dual output PWM Controller  
The IR3541 and CHL8325A/B are dual-loop digital  
multi-phase buck controllers that drive up to 5 phases.  
The IR3541 and CHL8325A/B are fully Intel® VR12 and AMD®  
SVI compliant on both loops and provides a Vtt tracking  
function for DDR memory.  
Phases are flexibly assigned between Loops 1 & 2  
Intel® VR12, AMD® 400kHz & 3.4MHz SVI and  
Memory modes  
Dual OCP support for I-spike enhanced AMD CPUs  
SMB_Alert Pin for Servers  
NVM storage saves pins and enables a small package size.  
PMBus Address pin or Variable Gate Drive  
(IR3541/CHL8325A)  
2nd Temperature Sense for VR12 Desktop  
(CHL8325B)  
The IR3541 and CHL8325A/B include the IR Efficiency  
Shaping Technology to deliver exceptional efficiency at  
minimum cost across the entire load range. IR Variable Gate  
Drive optimizes the MOSFET gate drive voltage as a function  
of real-time load current. IR Dynamic Phase Control  
adds/drops active phases based upon load current.  
The IR3541 and CHL8325A/B can be configured to enter  
1-phase operation and active diode emulation mode  
automatically or by command.  
Overclocking & Gaming Mode with Vmax setting  
Switching frequency from 200kHz to 1.2MHz per  
phase  
IR Efficiency Shaping Features including Variable  
Gate Drive (IR3541/CHL8325A only) and Dynamic  
Phase Control  
IR’s unique Adaptive Transient Algorithm (ATA), based on  
proprietary non-linear digital PWM algorithms, minimizes  
output bulk capacitors.  
Programmable 1-phase or 2-phase for Light Loads  
and Active Diode Emulation for Very Light Loads  
IR Adaptive Transient Algorithm (ATA) on both  
loops minimizes output bulk capacitors and  
system cost  
The I2C/PMBus interface can communicate with up to 16  
IR3541 and CHL8325A/B based VR loops. Device  
configuration and fault parameters are easily defined using  
the IR Intuitive Power Designer (DPDC) GUI and stored in  
on-chip NVM.  
Auto-Phase Detection with auto-compensation  
Per-Loop Fault Protection: OVP, UVP, OCP,  
OTP, CFP  
The IR3541 and CHL8325A/B also include numerous  
features like register diagnostics for fast design cycles and  
platform differentiation, truly simplifying VRD design and  
enabling fastest time-to-market with its “set-and-forget”  
methodology.  
I2C/SMBus/PMBus system interface for telemetry  
of Temperature, Voltage, Current & Power for  
both loops  
Non-Volatile Memory (NVM) for custom  
configuration  
Compatible with IR ATL and 3.3V Tri-state Drivers  
PIN DIAGRAM  
+3.3V supply voltage; -20ºC to 85ºC ambient  
operation  
Pb-Free, RoHS, 6x6 40-pin QFN, MSL2 package  
APPLICATIONS  
Intel ® VR12 & AMD® SVI based systems  
DDR Memory with Vtt tracking  
Overclocked & Gaming platforms  
Figure 1: IR3541 Package Top View  
1
June 21, 2013 | FINAL | V1.09  

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