Digital Multi-Phase GPU Buck Controller
CHL8266
FEATURES
DESCRIPTION
GPU-compliant Digital PWM Controller
The CHL8266 is a 6-phase digital synchronous buck
controller for regulation of high-performance GPU
platforms. The CHL8266 output VID table is fully compliant
with VR11.1 specifications.
Programmable 1-phase to 6-phase operation
Configurable switching frequency from 200 kHz to
1MHz per phase with accuracy better than 2%
The CHL8266 deploys a number of efficiency shaping
features. PSI can be programmed to be up to four phases
for optimum light-load efficiency, and the controller can
autonomously add/drop phases from mid to high and back
to mid current ranges to deliver 90+% efficiency across the
entire load range.
IR Dynamic Phase Control
1-phase to 2-phase PSI for Light Loads
Adaptive Transient Algorithm minimizes output
bulk capacitors
Enables Thermal Phase Balancing
IR’s unique Adaptive Transient Algorithm, based on non-
linear digital PWM algorithms, minimizes output bulk
capacitors.
SMBus interface for configuring and monitoring
Compatible with IR ATL Drivers and
Tri-state Drivers
CHL8266 supports NTC temperature sense to report
temperature and trigger VR HOT and OTP faults. Digital
thermal balancing allows proportional current imbalance
between phases.
Nine bytes of NVM storage available for
customer use
+3.3V supply voltage; 0ºC to 85ºC Ambient
operation
The CHL8266 provides extensive OVP, UVP, OCP and OTP
fault protection. Device and fault configuration parameters
are easily defined using the IR Digital Power Design Center
(DPDC) GUI and stored in on-chip non-volatile memory
(NVM).
RoHS Compliant, MSL level 1 package
APPLICATIONS
High performance GPU Voltage
Regulation solutions
The 2-pin SMBus interface can be used to monitor a variety
of operating parameters on CHL8266 based VRs.
High Current and High-Efficiency Applications
The CHL8266 truly simplifies VRD design and enables
fastest time-to-market with its “set-and-forget”
methodology.
PIN DIAGRAM
BASIC APPLICATION
12V
CHL8266
Power
Stage 1
48 47 46 45 44 43 42 41 40 39 38 37
VR_RDY
PWM1
VR_RDY
RCSP
RCSM
VCC
1
2
VCC
36
35
34
ISEN1
IRTN1
PWM6
PWM5
PWM4
PWM3
VR_HOT#
ENABLE
VR_HOT#
ENABLE
3
V_GPU
Power
Stage 2
VGPU
VRTN
4
33
32
PWM2
CHL8266
5
48 Pin
7mmx 7mm
QFN
ISEN2
IRTN2
SADDR
TP2
6
31
30
29
28
27
26
25
PWM2
PWM1
NC
SCL
.
.
.
SV_CLK
SV_DIO
7
TOP VIEW
8
RRES
VINSEN
TSEN
EN
SDA
Power
Stage 5
9
VCC
PWM4
GND
10
11
12
NC
ISEN4
IRTN4
VR_HOT
V18A
VR_READY
3.3V
VCC
Power
Stage 6
PWM1_L2
13 14 15 16 17 18 19 20 21 22 23 24
ISEN1_L2
IRTN1_L2
Figure 2: CHL8266 Package Top View
Figure 1: CHL8266 Basic Application Circuit
1
October 12, 2011 | FINAL | V1.05