CDP1853,
CDP1853C
March 1997
N-Bit 1 of 8 Decoder
Features
Description
The CDP1853 and CDP1853C are 1 of 8 decoders designed for
use in general purpose microprocessor systems. These
devices, which are functionally identical, are specifically
designed for use as gated N-bit decoders and interface directly
with the 1800-series microprocessors without additional compo-
nents. The CDP1853 has a recommended operating voltage
range of 4V to 10.5V, and the CDP1853C has a recommended
operating voltage range of 4V to 6.5V.
• Provides Direct Control of Up to 7 Input and 7 Output
Devices
• CHIP ENABLE (CE) Allows Easy Expansion for Multi-
level I/O Systems
Ordering Information
PKG.
When CHIP ENABLE (CE) is high, the selected output will be
true (high) from the trailing edge of CLOCK A (high-to-low tran-
sition) to the trailing edge of CLOCK B (high-to-low transition).
All outputs will be low when the device is not selected (CE = 0)
and during conditions of CLOCK A and CLOCK B as shown in
Figure 2. The CDP1853 inputs N0, N1, N2, CLOCK A, and
CLOCK B are connected to an 1800-series microprocessor out-
puts N0, N1, N2, TPA, and TPB respectively, when used to
decode I/O commands as shown in Figure 5. The CHIP
ENABLE (CE) input provides the capability for multiple levels of
decoding as shown in Figure 6.
PACKAGE TEMP. RANGE
5V
-40 C to +85 C CDP1853CE CDP1853E E16.3
CDP1853CEX E16.3
-40 C to +85 C CDP1853CD CDP1853D D16.3
CDP1853CDX D16.3
10V
NO.
o
o
PDIP
Burn-In
SBDIP
Burn-In
-
o
o
-
The CDP1853 can also be used as a general 1 of 8 decoder for
I/O and memory system applications as shown in Figure 4.
The CDP1853 and CDP1853C are supplied in hermetic 16-lead
dual-in-line ceramic (D suffix) and plastic (E suffix) packages.
TRUTH TABLE
Pinout
CDP1853 Functional Diagram
16 LEAD DIP
TOP VIEW
CE
1
CL A
CL B
EN
4
OUT 0
0
0
1
1
X
0
1
0
1
X
Qn-1†
2
5
6
N0
N1
N2
OUT 1
OUT 2
OUT 3
OUT 4
OUT 5
OUT 6
OUT 7
CLK A 1
N0 2
16 VDD
1
1
0
1
0
15 CLK B
14 N2
7
3
1 OF 8
DECODER
1
N1 3
12
11
10
9
OUT 0 4
OUT 1 5
OUT 2 6
OUT 3 7
13 CE
1
14
12 OUT 4
11 OUT 5
10 OUT 6
9 OUT 7
0
EN
13
CE
1
N2
0
N1
0
N0
EN
1
0
1
0
0
0
0
0
0
0
0
1
0
1
0
0
0
0
0
0
0
2
0
0
1
0
0
0
0
0
0
3
0
0
0
1
0
0
0
0
0
4
0
0
0
0
1
0
0
0
0
5
0
0
0
0
0
1
0
0
0
6
0
0
0
0
0
0
1
0
0
7
0
0
0
0
0
0
0
1
0
VSS
8
0
1
0
1
0
1
0
1
X
Qn
0
0
1
CLOCK
A
(TPA)
0
1
1
0
1
1
1
0
1
15
CLOCK
B
(TPB)
1
0
1
1
1
1
1
1
1
FIGURE 1.
X
X
0
1 = High level, 0 = Low level, X = Don’t care
† Qn-1 = Enable remains in previous state.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
File Number 1189.2
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